IBM最近展示了如何將相變化內(nèi)存(PCM)整合到固態(tài)內(nèi)存階層架構(gòu)(hierarchy)，并展示了第一款采用 PCIe 接口的相變化內(nèi)存儲(chǔ)存系統(tǒng)主板原型；在下一代主流內(nèi)存技術(shù)爭(zhēng)霸戰(zhàn)中，相變化內(nèi)存似乎已經(jīng)占據(jù)優(yōu)勢(shì)。 在一場(chǎng)于2014年非揮發(fā)性內(nèi)存研討會(huì)(2014 Non-Volatile Memory Workshop)的簡(jiǎn)報(bào)中，IBM介紹了相變化內(nèi)存儲(chǔ)存系統(tǒng)架構(gòu)，并以閃存固態(tài)硬盤(SSD)做為比較；在各方面的比較上，相變化內(nèi)存都略勝閃存一籌。此外該公司提出了一款服務(wù)器系統(tǒng)設(shè)計(jì)，以結(jié)合閃存數(shù)組與相變化內(nèi)存數(shù)組的內(nèi)存階層架構(gòu)來(lái)取代硬盤(HDD)。 “我們是以閃存固態(tài)硬盤與相變化內(nèi)存PCIe儲(chǔ)存卡，在兩種設(shè)備的系統(tǒng)層級(jí)進(jìn)行比較；”IBM儲(chǔ)存系統(tǒng)研究小組成員Ioannis Koltsidas表示，該公司所合作的希臘帕特雷大學(xué)(University of Patras)，以古希臘神話中的英雄特修斯(Theseus)來(lái)為相變化內(nèi)存儲(chǔ)存卡命名。 而研究人員是拿相變化內(nèi)存PCIe儲(chǔ)存卡與兩款閃存固態(tài)硬盤──包括一款企業(yè)級(jí)產(chǎn)品與一款消費(fèi)性產(chǎn)品──進(jìn)行比較，發(fā)現(xiàn)兩款固態(tài)硬盤的訪問(wèn)時(shí)間，分別是相變化內(nèi)存儲(chǔ)存卡的12倍與275倍。

IBM儲(chǔ)存系統(tǒng)研究小組成員Ioannis Koltsidas展示相變化儲(chǔ)存系統(tǒng)電路板原型
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雖然相變化內(nèi)存芯片在 2012年左右就已經(jīng)問(wèn)世，但實(shí)際布署的案例非常少，也聽(tīng)到業(yè)界出現(xiàn)少數(shù)對(duì)其可靠性的抱怨；無(wú)論如何，IBM顯然十分看好相變化內(nèi)存前景，但人們可能也會(huì)認(rèn)為，相變化內(nèi)存需要先解決一些技術(shù)上的問(wèn)題。 相變化內(nèi)存的最大優(yōu)勢(shì)在于訪問(wèn)速度高于閃存，但仍稍遜于DRAM；此外相變化內(nèi)存也擁有非揮發(fā)性。而相變化內(nèi)存的正常輸入/輸出(I/O)吞吐量，在硬盤的每秒I/O運(yùn)作效率降低時(shí)可維持上升，有機(jī)會(huì)取代目前閃存所扮演的角色。 快 閃內(nèi)存正面臨擴(kuò)充性(scalability)的問(wèn)題，重復(fù)寫入次數(shù)最多約為1萬(wàn)次；相變化內(nèi)存的可擴(kuò)充性則不斷提升，重復(fù)讀寫次數(shù)可高達(dá)1,000 萬(wàn)次──而若是透過(guò)前向糾錯(cuò)(forward error correction)技術(shù)，甚至可將重復(fù)讀寫次數(shù)提升到10兆(trillion)次。

IBM表示，相變化內(nèi)存(藍(lán)色部分)能整合至大多數(shù)服務(wù)器與儲(chǔ)存系統(tǒng)的內(nèi)存階層中
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相 變化內(nèi)存是采用在兩個(gè)電極之間夾著硫化物合金(chalcogenidic alloy)的三明治結(jié)構(gòu)，高電流會(huì)將硫化物合金轉(zhuǎn)為非晶(amorphous)型態(tài)(代表0)，而中電流則會(huì)將之轉(zhuǎn)換為結(jié)晶型態(tài)(代表1)，低電流則允許其狀態(tài)被讀取。其0與1的程序化時(shí)間分別為70納秒(nanosecond)與120納秒；IBM所測(cè)試的儲(chǔ)存系統(tǒng)之相變化內(nèi)存采用90納米制程，時(shí)脈頻率66MHz。 本文授權(quán)編譯自EE Times，版權(quán)所有，謝絕轉(zhuǎn)載 編譯：Judith Cheng 參考英文原文：IBM Hawks PCM for Storage，by R. Colin Johnson

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{pagination} IBM Hawks PCM for Storage R. Colin Johnson PORTLAND, Ore. -- IBM recently demonstrated how to integrate phase change memory (PCM) into a solid-state memory hierarchy, and it has shown its first PCIe-based prototype board for storage systems. It's looking like speed and the ancient Greek heroes are on PCM's side. In a presentation at the 2014 Non-Volatile Memory Workshop, IBM described its architecture, compared it to flash-based solid-state drives (SSDs), and proposed a server system that eliminated the hard-disk drive (HDD) in favor of a memory hierarchy using both flash-based arrays and PCM-based arrays. In comparisons, the PCM-based arrays handily beat flash. Ioannis Koltsidas, an IBM storage systems research staff member, shows his prototype board that outperforms flash alone by adding phase change memory (PCM). (Source: IBM) "The comparison was between flash SSD and our PCM PCIe card -- it was a comparison at the system level of the two storage devices," Ioannis Koltsidas, a member of the IBM storage systems research staff, told EE Times. Working with the University of Patras in Greece, which helped name the card Theseus after a hero in Greek mythology, the researchers compared the PCM-based PCIe card with two flash SSDs -- an enterprise-grade flash SSD and a consumer-grade flash SSD. "We found the times for the two flash SSDs to be 12x and 275x longer than for the PCM PCI-e card." Though PCM memory chips have been around since 2012, there have been very few deployments and quite a few complaints about reliability. Nevertheless, IBM appears to be gung ho about the possibilities of PCM-based memories, one would assume, after the bugs are worked out. PCM (blue) can fit into many slots in the memory hierarchy for servers and storage systems, according to IBM. The biggest advantage of PCM over flash is that its performance is higher than flash, though not as high as DRAM, plus it enjoys the nonvolatility of flash. Also, PCM normalized input/output (I/O) throughput is on the rise at a time when HDD I/O operations per second are waning. Today flash is filling the gap, but PCM could take over that job. Flash is also facing scalability problems and can only be rewritten about 10,000 times at the most. PCM's scalability is on the rise, and it can be rewritten at least 10 million times -- or, with forward error correction, at least 10 trillion times. PCM uses a chalcogenidic alloy sandwiched between two electrodes. A high current turns the chalcogenidic alloy amorphous (representing a 0), whereas a medium current turns it crystalline (representing a 1), and a low current allows its state to be read out. Programming times for 0s and 1s are 70 nanoseconds and 120 nanoseconds, respectively. IBM's tests used PCM memories fabricated at a relaxed feature size of 90 nanometers and a clock frequency of 66 megaHertz.