根據(jù)Semico Research的報(bào)告顯示，采用28nm制程的系統(tǒng)級(jí)芯片(SoC)設(shè)計(jì)成本較前一代40nm制程節(jié)點(diǎn)增加了78%，此外，軟件成本增加的比重更高，提高約一倍以上。
Semicon估計(jì)，推出系統(tǒng)芯片所需的軟件開發(fā)成本，目前已經(jīng)遠(yuǎn)高于IC設(shè)計(jì)的成本了。
Semico Research指出，盡管在28nm節(jié)點(diǎn)的SoC設(shè)計(jì)成本比40nm節(jié)點(diǎn)時(shí)提高了78%以上，但用于編寫與檢查所需軟件成本更上漲了102%。
軟件所需負(fù)擔(dān)的成本預(yù)計(jì)每年都將增加近一倍。Semico預(yù)測，在10nm芯片制程節(jié)點(diǎn)以前，每年用于SoC軟件開發(fā)的成本年復(fù)合成長率(CAGR)約79%。整合分離式IP模組于當(dāng)代SoC中的成本年復(fù)合成長率(CAGR)也達(dá)到了77.2%。
對(duì)于芯片開發(fā)商而言，好消息是Semico公司預(yù)期芯片設(shè)計(jì)成本的增加將較緩和。20nm節(jié)點(diǎn)時(shí)的SoC設(shè)計(jì)成本預(yù)計(jì)將較28nm節(jié)點(diǎn)時(shí)增加48%，到了14nm時(shí)將增加31%，而在10nm節(jié)點(diǎn)時(shí)增加約35%。
由于軟件負(fù)擔(dān)以及整合多方IP核心的成本提高，預(yù)計(jì)在突破新制程節(jié)點(diǎn)時(shí)的先進(jìn)多核心設(shè)計(jì)將達(dá)到最高成本。Semico表示，同一制程節(jié)點(diǎn)時(shí)所衍生的SoC設(shè)計(jì)成本都只是首次開發(fā)成本的一小部份。
同時(shí)，專為某一既有節(jié)點(diǎn)建置的新設(shè)計(jì)，其成本將隨著時(shí)間的進(jìn)展逐漸大幅降低。在14nm節(jié)點(diǎn)實(shí)現(xiàn)商用化以前，45nm節(jié)點(diǎn)高性能多核心SoC設(shè)計(jì)成本的CAGR為-12.7%。
Semico并估計(jì)以20nm制造的芯片售價(jià)約20美元，因而必須達(dá)到920萬片的出貨量，實(shí)現(xiàn)超過1.8億美元的營收，方能取得盈虧平衡。
編譯：Susan Hong
參考原文：28-nm SoC development costs doubled over 40-nm，by Peter Clarke
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The cost of designing system-on-chip silicon at 28-nm went up by 78 percent over the previous node, but the software cost was larger and more than doubled, says Semico Research.
Semico reckons the cost of developing the software that it is necessary to ship with system chips is now greater than the cost of the IC design.
While the cost of SoC design at the 28-nm node is 78 percent more than it was at the 40-nm node the cost of writing and checking the necessary software went up by 102 percent, the market researcher claims.
And the software burden will increase close to doubling in cost every year. Semico predicts a compound annual growth rate for SoC software development of 79 percent through to the arrival of the 10-nm chip manufacturing node. The cost to integrate discrete IP blocks used in contemporary SoCs is also rising showing a CAGR of 77.2 percent, Semico said.
The good news for chip developers is that Semico forecasts that the growth of chip design cost will be lower. Semico said it expects SoC design costs to increase 48 percent at the 20-nm node compared with the 28-nm node. They are expected to increase by a further 31 percent at the 14-nm node and by 35 percent at the 10-nm node.
Because of the high software burden and the cost of integrating IP cores from multiple sources the highest costs are seen in advanced multicore designs that break in a new process node. Derivative SoC designs at the same process node are a fraction of the cost of those first-time designs Semico said.
At the same time novel designs that are designed for an established manufacturing node will show a marked reduction in cost over time. The costs for an advanced performance multicore SoC design, continuously done at the 45-nm node will experience a negative CAGR of 12.7 percent by the time the 14-nm process node becomes commercially available.
Semico estimates that an made in 20-nm silicon that sells for $20 must ship 9.2 million units and achieve more than $180 million in revenue to breakeven.
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責(zé)編：Quentin
