三星(Samsung)將在明年二月的國際固態(tài)電路大會(ISSCC)中，展示采用 ARM big.little 概念的移動應(yīng)用處理器。 這是少數(shù)將在該會議大披露的新款微處理器，但包括英特爾(Intel)的 Haswell 和 Nvidia 的丹佛計劃(Project Denver)，都很明顯地缺席。不過，英特爾和 Nvidia 都將就新的芯片到芯片連接提出最新論文，展示他們對未來處理器的規(guī)劃。 三星將揭露具有兩個四核心叢集的 28nm SoC 詳細資料。其中一個叢集執(zhí)行在1.8GHz，具有2MB L2 快取，主要針對高性能應(yīng)用；另一款速度為1.2GHz，可用于調(diào)節(jié)能源效率。 該芯片與 ARM 所提出之采用 32位 A15 和 A7 核心的 big.little 架構(gòu)相同。今年10月時，ARM曾表示這種方法提供了比預(yù)期還要高的效益，未來將廣泛應(yīng)用在智能手機中。 Linley Group 資深分析師Kevin Krewell表示，三星將推出首款 big.little 處理器。 A7 核心應(yīng)該能處理大多數(shù)智能手機的任務(wù)，而A15核心則處理需要高性能的需求，如游戲。 而其它如高通(Qualcomm)、 Nvidia 和其它預(yù)計2013年推出，將與英特爾 22nm Haswell 在平板市場競爭的處理器則并未計劃在 ISSCC 上披露。根據(jù)過去經(jīng)驗，英特爾在會議上提出的論文向來與處理器無關(guān)。 不過，這家 x86 巨擘將描述一款頻寬達1Tb的可擴展64信道芯片到芯片互連。 該鏈路使用多個2~16Gb/s信道，執(zhí)行在0.8~2.6 pJ /bit，采用32nm CMOS制程，總總線功耗為2.6W 這篇文章介紹了英特爾研究院(Intel Labs)的研究成果。英特爾實驗室資深首席工程師Bryan Casper表示，該論文描述了使用Samtec的micro-twinax線路，以及 Ardent Concepts 的連接器來連接Tb/s等級的芯片，否則功耗可能會拉升至20W。 Casper表示，直徑1到2mm的線束將是“我們在跨越移動和 服務(wù)器應(yīng)用時，向前邁進的重要技術(shù)。次pJ /bit I/O非常重要，因為這是快速開啟和關(guān)閉I/O連接的關(guān)鍵?！? Nvidia將描述一款20Gb/s的串行芯片到芯片28nm CMOS，它采用0.9V電源，電源效率0.54pJ/b。這項互連技術(shù)可能會與Nvidia的丹佛計劃整合，也可能應(yīng)用在從筆電到超級計算機等所有ARM和繪圖核心處理器系列中。 此外，中國科學(xué)院計算技術(shù)研究所(ICT)將提出新版龍芯3B處理器 (Godson 3B)，該組件采用32nm。在此之前，ICT展示過八核心65nm CPU，并建議直接跨越到32nm。 在 ISSCC上，工程師將詳細介紹Godson-3B1500，這是一款32nm high-K金屬閘極組件，在1.35 GHz、40W條件下可提供172.8 GFLOPS性能。在同等功耗條件下，新處理器性能較65nm版本的128 Gflops有顯著提升，這主要歸功于新制、架構(gòu)和電路的改良。 在其它論文中，德州儀器(TI)和麻省理工學(xué)院(MIT)將提出一款200MHz的影像譯碼器，可符合高效影像編碼標準，提供每秒249M畫素性能。它支持3,840 × 2,160畫素分辨率，在0.9V時耗電76mW。 瑞薩(Renesas)將描述一款整合手機芯片，其中包含28nm雙核心1.5GHz CPU、 LTE/HSPA + 基頻調(diào)制解調(diào)器處理器、繪圖加速器和電源管理單元。 AMD, IBM和甲骨文(Oracle)則將分別就其 Jaguar, zSeries 和 Sparc T5 發(fā)表論文。 本文授權(quán)編譯自EE Times，版權(quán)所有，謝絕轉(zhuǎn)載 編譯： Joy Teng 參考英文原文：ISSCC: Samsung big.little, but no Intel, Nvidia CPUs，by Rick Merritt

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{pagination} ISSCC: Samsung big.little, but no Intel, Nvidia CPUs Rick Merritt SAN JOSE, Calif. – Samsung will describe the first mobile applications processor to use ARM’s big.little concept at the International Solid-State Circuits Conference in February. That's one of only a few major new microprocessor disclosures at the semiconductor industry's premier conference where Intel’s Haswell and Nvidia’s Project Denver parts are noticeably absent. However, both Intel and Nvidia will deliver papers on new chip-to-chip links that may provide an oblique view on their future processor plans. Samsung will detail a 28-nm SoC with two quad-core clusters. One cluster runs at 1. 8 GHz, has a 2 MByte L2 cache and is geared for high performance apps; the other runs at 1.2 GHz and is tuned for energy efficiency. The chip clearly parallel’s ARM’s description of a big.little architecture using its 32-bit A15 and A7 cores. In October, ARM said the approach is delivering greater than expected benefits and expects it will become widely used in smartphones. “We expect the Samsung part is the first big.little processor,” said Kevin Krewell, senior analyst with market watcher Linley Group (Mountain View, Calif.). “The A7 cores should be capable of handling most [smartphone] tasks, with the A15 cores only required for maximum performance needs, like video games,” he said. The chip and ones like it from Qualcomm, Nvidia and others will roll out in 2013, competing for sockets in tablets with Intel’s 22-nm Haswell, which will not be described at ISSCC. In a departure from past years, Intel will present no processor papers at the event. However, the x86 giant will describe a scalable 64-lane chip-to-chip interconnect with 1 Tbit/s aggregate bandwidth. The link uses multiple 2-16 Gbit/s channels running at power efficiencies of 0.8 to 2.6 pJ/bit in 32nm CMOS with a total bus-level power consumption of 2.6 W. The paper describes research at Intel Labs that is not necessarily related to a clustering interconnect the company announced in September for future x86 and Atom server processors. It describes research using so-called micro-twinax wiring from Samtec, and connectors from Ardent Concepts to link chips at Tbit/s rates that otherwise might draw up to 20 W, according to co-author Bryan Casper, a senior principal engineer overseeing I/O research at Intel Labs. The 1 to 2 millimeter diameter wire bundles will be “a very important technology for us going forward for some segments” spanning mobile and server apps, said Casper. “Sub picojoule per bit I/O is really important, as are fast on and off I/O links." Separately, NVidia will describe a 20 Gbit/s serial die-to-die link made in 28-nm CMOS. It runs on a 0.9 V supply and has power efficiency of 0.54pJ/b. The interconnect might be part of Nvidia’s Project Denver, a still secretive family of processors merging ARM and graphics cores for everything from notebooks to supercomputers. Godson update “It could be part of Project Denver or a technology to connect multiple GPUs together for Tesla-based supercomputer support,” said Krewell of Linley Group. “I haven't heard any details of how Project Denver is proceeding, but Nvidia certainly needs to develop high performance interfaces that can connect arrays of Project Denver heterogeneous processors." Nvidia’s graphics chips are already widely used in massive clusters for supercomputers, including the world’s current fastest system called Titan. Separately, China’s Institute of Computing Technology will describe a new version of the Godson 3B processor made using a 32-nm process. Previously ICT showed eight-core 65-nm CPUs and suggested it would leapfrog to 28-nm designs. At ISSCC, engineers will detail Godson-3B1500, a 32-nm high-K, metal gate part delivering 172.8 Gflops when running at 1.35 GHz at 40 W. That’s up from 128 Gflops for the 65-nm version also drawing 40 W, thanks to the new process as well as architecture and circuit enhancements. Among other papers, Texas Instruments and MIT will describe a 200-MHz video decoder implementing the High-Efficiency Video Coding draft standard to deliver 249 Mpixels/s. It enables 3840 x 2160 pixel resolution while consuming 76 mW at 0.9 V. Renesas will describe a 28-nm integrated handset SoC with a dual-core 1.5 GHz CPU, an LTE/HSPA+ baseband modem processor, graphics accelerators and a power management unit. AMD, IBM and Oracle will present papers on their Jaguar, zSeries and Sparc T5 processors already described in August at Hot Chips.