無晶圓廠FPGA供貨商 Achronix Semiconductor Corp. 開始向芯片公司授權(quán)其FPGA技術(shù)，將業(yè)務(wù)范圍擴(kuò)展到了廣大的 SoC市場。 Achronix 表示，將繼續(xù)推出采用英特爾(Intel)制程制造的高性能 22nm FPGA ，但另一方面也將努力打入包括移動(dòng)和消費(fèi)應(yīng)用在內(nèi)的大量市場。 Achronix 的 22i Speedster FPGA 采用英特爾 22nm FinFET 制程，具備多種高速數(shù)據(jù)通信接口硬聯(lián)機(jī)，包括10/40/100G以太網(wǎng)絡(luò)MAC 、100Gb Interlaken 信道、PCI Express和 DDR3內(nèi)存信道等。 本季，該公司還將發(fā)布一款具備60億個(gè)晶體管的FPGA ── HD1000。Achronix 公司創(chuàng)辦人暨主席 Lofton Holt 還透露， Achronix 將于2013年推出具備90億個(gè)晶體管的FPGA，將采用相同的22nm FinFET制程。 不過，這些大容量FPGA都銷定產(chǎn)量相對較小的高階應(yīng)用，如通信基礎(chǔ)設(shè)施等，Holt說。隨著越來越多SoC項(xiàng)目的上市時(shí)程落后，Holt認(rèn)為，下一代SoC必然會(huì)是可編程的。 EFPGA FPGA向來是以單一封裝組件提供板級的可編程特性。Holt表示，該公司已嘗試將獨(dú)立的邏輯和FPGA芯片整合在單一封裝中，但不太成功。他認(rèn)為，芯片級的整合會(huì)是下一個(gè)進(jìn)化步驟。 Holt在說明Achronix 的IP產(chǎn)品時(shí)介紹了三款嵌入式FPGA (eFPGA)宏，它們帶有100,000及100萬之間的有效閘極，面積約2.1到19.2mm2，采用英特爾22nm FinFET制程。然而，Holt承認(rèn)，目前許多與該公司接洽的客戶都正在尋求自定義的FPGA架構(gòu)(FPGA fabrics)。 Holt表示：“根據(jù)不同的性能和功耗要求，針對這些架構(gòu)組成部份的芯片面積可減少高達(dá)40%。我們還計(jì)劃在2013年支持先進(jìn)的TSMC制程?！? Holt表示，其IP業(yè)務(wù)的代工業(yè)者目前未定，但其所有的IP授權(quán)的相關(guān)客戶均鎖定TSMC。他接著表示，由英特爾制造的FPGA芯片也可能讓該公司更快獲得客戶，將產(chǎn)品推向市場。 然而，目前有關(guān)其FPGA fabric的問題之一，是如何連接到芯片總線，以確保能為所有設(shè)計(jì)團(tuán)隊(duì)都可能嘗試解決的中斷來提供適合的額外資源。 Holt表示，Achronix已規(guī)劃了三種可支持其FPGA技術(shù)的EDA流程。第一種是標(biāo)準(zhǔn)流程，工程師們可在RTL級對Achronix FPGA做編程。第二種是整合的SoC/FPGA設(shè)計(jì)流程，可支持在SoC內(nèi)增加FPGA fabric并進(jìn)行編程。第三種EDA流程將進(jìn)一步擴(kuò)展FPGA fabric中的可編程性，以支持可重配置功能。 Achronix 打算在2014年首次公開募股。為實(shí)現(xiàn)此一目標(biāo)，Holt估計(jì)該公司將需要1億美元的年銷售額和70%以上的毛利率。“我要維持高利潤，并進(jìn)入手機(jī)市場?！彼f。 本文授權(quán)編譯自EE Times，版權(quán)所有，謝絕轉(zhuǎn)載 編譯： Joy Teng 參考英文原文：Achronix shifts gears, offers FPGA IP for SoCs ，by Peter Clarke

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{pagination} Achronix shifts gears, offers FPGA IP for SoCs Peter Clarke BRATISLAVA, Slovakia--Fabless FPGA vendor Achronix Semiconductor Corp. has jumped into the SoC market by offering to license its FPGA technology to chip companies. Achronix (Santa Clara, Calif.) will continue to market high-performance 22-nm FPGAs built by Intel Corp. on a foundry basis. But, in an effort to get into higher volume markets like mobile and consumer applications, Achronix will also license its FPGA fabric to serve as an insurance policy for SoC chip makers against a change in a standard or the need for a respin of the silicon, said John Lofton Holt, Achronix founder and chairman. Holt announced the addition of licensing to Achronix' business model to industry executives gathered here Thursday (Oct. 4) at the International Electronics Forum organized by Future Horizons. To date, Achronix has presented itself as a high-performance FPGA provider seeking to eclipse FPGA market leaders Altera Corp. and Xilinx Inc. Achronix drew attention when it switched foundries to go with Intel in an effort to claim the higher ground. Achronix' 22i Speedster FPGAs are manufactured using Intel's 22-nm FinFET manufacturing process and come with a variety of high-speed data communications interfaces hardwired. These include 10/40/100G Ethernet MACs, 100Gbit Interlaken channels, PCI Express and DDR3 memory channels. The HD1000 is a 6 billion transistor FPGA that will become available this quarter. Holt said Achronix would tape-out a 9 billion transistor FPGA in 2013 aimed at the same 22-nm FinFET manufacturing process. But while high-capacity FPGAs have their place, the space is reserved for relatively low-volume, high-end applications such as communications infrastructure, Holt said. As increasing numbers of SoC projects are delivered behind schedule and need multiple spins, Holt said. Silicon programmability is becoming a necessity for next-generation SoCs, Holt argued. eFPGA FPGA programmability has traditionally been supplied at the board level with a separate packaged device. Holt said attempts had been made to include separate logic and FPGA die in one package but with less success. Die-level integration is the next stage of that integration evolution, Holt argued. By way of an illustration of the Achronix IP offering Holt flashed up three embedded FPGA (eFPGA) macros with between 100,000 and 1 million effective gates and occupying between 2.1 and 19.2 square millimeters in Intel's 22-nm FinFET process. However, Holt admitted that most of the customers Achronix is engaged with today are looking for custom FPGA fabrics. In his presentation Holt said: "Depending on the performance and power requirements, the die area for some of these fabric components can be reduced by up to 40 percent. We are also planning to support advanced TSMC processes in 2013." Holt also admitted that while its IP business line will be foundry agnostic, all its present IP licensees are targeting TSMC. He added that Achronix could probably get customers to market faster with an Intel-produced chip as the FPGA fabric is fully characterized. "Intel foundry is not averse to this if the volumes are right," Holt said. However, doubts about the approach remain. One is how to connect the FPGA fabric into the on-chip bus to guarantee to provide suitable additional resources for all the disruptions the design team might be trying to insure against. Holt said Achronix now envisions three EDA design flows in support of its FPGA technology. The first is the standard flow that allows engineers to program Achronix FPGAs down to the RTL level, which Achronix has offered since 2008. The second is an integrated SoC/FPGA design flow to support the addition of FPGA fabric in SoCs and allow the fabric to be programmed. The third EDA flow will extend that FPGA fabric programmability to users to support functional reconfigurability. Achronix' current business plan of record is to conduct an initial public offering in 2014. To achieve that, Holt reckons the company will need $100 million of annual sales and 70-plus percent gross margins. "I want to stay high margin, to get into handsets," he said.