“市場(chǎng)占有率”在內(nèi)存半導(dǎo)體市場(chǎng)中至關(guān)重要。“內(nèi)存”可說(shuō)是電子產(chǎn)業(yè)中最反復(fù)多變的領(lǐng)域之一；同時(shí)，價(jià)格、供給與需求的起起落落還使得亞洲、歐洲與北美等多家公司被逼至絕境，包括臺(tái)灣的幾家供貨商，以及幾年前由英飛凌科技(Infineon Technologies)獨(dú)立而出的奇夢(mèng)達(dá)(Qimonda)公司。 “規(guī)模”在此領(lǐng)域中也相當(dāng)重要。一家公司規(guī)模越大，就越容易提供資本開(kāi)支，能承受?chē)?yán)峻的產(chǎn)品生命周期，并取得更高的市占率。這就是為什么收購(gòu)爾必達(dá)公司(Elpida Memory)的這項(xiàng)交易決定對(duì)于美光公司(Micron Technology)來(lái)說(shuō)格外重要。過(guò)去十多年來(lái)，這是美光公司第一次掌握了得以提升其市占率的大好機(jī)會(huì)，同時(shí)也增加其于另一波市場(chǎng)動(dòng)蕩后仍得以生存的機(jī)率。 根據(jù)市調(diào)機(jī)構(gòu) IHS 指出，這項(xiàng)收購(gòu)協(xié)議同時(shí)也使得美光公司成為全球 DRAM 市場(chǎng)的第2大廠。IHS指出，美光公司將可占有大約四分之一的市場(chǎng)銷(xiāo)售量，使其位居于領(lǐng)先韓國(guó)海力士半導(dǎo)體(Hynix Semiconductor Inc.)的位置。在該市場(chǎng)長(zhǎng)期占主導(dǎo)地位的三星電子(Samsung Electronics)仍握有41%的最大市占率。 IHS公司負(fù)責(zé) DRAM 與內(nèi)存研究的資深首席分析師Mike Howard表示，收購(gòu)爾必達(dá)對(duì)于美光公司目前在 DRAM 領(lǐng)域的地位具有重大的推升作用。 美光公司的市占率與DRAM制造產(chǎn)能可望提升將近一倍。再者，美光還取得了一些優(yōu)越的行動(dòng)DRAM技術(shù)，能夠大幅地改善產(chǎn)品組合。25億美元的收購(gòu)價(jià)格合 理，而且也不至于對(duì)于美光公司的現(xiàn)金狀況帶來(lái)任何不利的影響。雖然這項(xiàng)交易至少還需要六個(gè)月的時(shí)間才完成收購(gòu)，但I(xiàn)HS預(yù)期一旦整并行動(dòng)展開(kāi)后，很快地就 能完成轉(zhuǎn)型與整合。 對(duì)于美光公司與其它主要的 DRAM 供貨商而言，這項(xiàng)收購(gòu)交易還帶來(lái)了其它的好處。爾必達(dá)公司先前曾經(jīng)宣布進(jìn)入破產(chǎn)程序，此舉大幅降低了廠房利用率與供應(yīng)，因而使得DRAM價(jià)格趨于穩(wěn)定。 IHS公司表示，在爾必達(dá)申請(qǐng)破產(chǎn)保護(hù)之前，“2011年在 DRAM 制造產(chǎn)能過(guò)剩，使得價(jià)格被壓低并造成營(yíng)收下降的情況下， DRAM 產(chǎn)業(yè)持續(xù)處于低迷?！币虼耍谶@項(xiàng)收購(gòu)交易完成后，美光預(yù)計(jì)將進(jìn)一步減少爾必達(dá)的制造產(chǎn)能。 根據(jù)IHS公司表示：“由爾必達(dá)破產(chǎn)及隨后被美光公司收購(gòu)導(dǎo)致DRAM市場(chǎng)進(jìn)一步趨于整并，將為DRAM帶來(lái)新的穩(wěn)定價(jià)格，從而有助于帶動(dòng)這個(gè)市場(chǎng)的復(fù)蘇成長(zhǎng)?！? 預(yù)計(jì)今年全球 DRAM 產(chǎn)業(yè)營(yíng)收將達(dá)到305億美元，較2011年的296億美元成長(zhǎng)3.3%。盡管目前所看到的成長(zhǎng)似乎很小，但相較于去年出現(xiàn)減少25%的驚人數(shù)字時(shí)，2012年的營(yíng)收增加仍是令人慶幸的正面發(fā)展。 對(duì)于美光公司而言，收購(gòu)爾必達(dá)雖然被為是一項(xiàng)積極的行動(dòng)，但無(wú)疑地也將會(huì)對(duì)于OEM等小型廠商帶來(lái)壓力。像是南亞(Nanya)與華邦(Windbond) 等市占率低于5%的公司將會(huì)發(fā)現(xiàn)越來(lái)越難以和既有的廠商競(jìng)爭(zhēng)。即使是海力士也很難全身而退。 DRAM 生產(chǎn)是一項(xiàng)高度資本密集的業(yè)務(wù)，供貨商所在的位置越高，越容易為廠房及其它生產(chǎn)活動(dòng)取得穩(wěn)定的財(cái)務(wù)融資。 美光與爾必達(dá)的整并，還將使仍致力于解決投資人與金融業(yè)者等問(wèn)題的海力士處于較不利的位置。但海力士可能因此讓位于規(guī)模較小的競(jìng)爭(zhēng)者，使其提高市占率嗎？我想不太可能，因 為其它的競(jìng)爭(zhēng)對(duì)手們目前的市占率都相當(dāng)小，海力士不至于大幅改變其現(xiàn)有位置。而今，美光公司正處于一個(gè)更有利的市場(chǎng)位置，更有機(jī)會(huì)遠(yuǎn)遠(yuǎn)拉開(kāi)其與海力士之間的距離。 想要迎頭趕上三星公司，則又是另一個(gè)重大的行動(dòng)。這家韓國(guó)巨擘──三星電子一向?qū)τ诟?jìng)爭(zhēng)對(duì)手采取各種施壓策略行動(dòng)絕 不手軟，而且該公司還計(jì)劃要在今年加碼資本投資力度。無(wú)論美光公司目前的現(xiàn)金位置有多么穩(wěn)健，在接下來(lái)的幾年內(nèi)，收購(gòu)爾必達(dá)的協(xié)議都將為其帶來(lái)現(xiàn)金債務(wù)， 因此，美光公司在現(xiàn)階段仍無(wú)力負(fù)擔(dān)或跟進(jìn)。目前，美光公司將只能暫時(shí)居于市場(chǎng)第二的位置。 編譯：Susan Hong 本文授權(quán)編譯自EBN Online，版權(quán)所有，謝絕轉(zhuǎn)載 本文下一頁(yè)：參考英文原文：Micron Rising, But Can It Catch Samsung?，by Bolaji Ojo, Editor in Chief

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{pagination} Micron, Samsung seek hybrid memory spec Dylan McGrath SAN FRANCISCO—Micron Technology Inc. and South Korea's Samsung Electronics Co. Ltd. Thursday (Oct. 6) announced the formation of an open consortium around hybrid memory cube (HMC), a technology that brings DRAM memory and logic processes together into one package to offer potential power efficiency, bandwidth, density and scalability advantages over traditional DRAM. The goal of the Hybrid Memory Cube Consortium is to establish HMC as a new memory standard, according to Micron and Samsung. The consortium will begin meeting this month to develop a specification, which they expect to be released in 2012, the companies said. The group plans to share an early draft of an HMC interface specification with OEMs, ASIC developers and other firms at an early point for review, discussion and development, according to Scott Graham, general manager of DRAM marketing at Micron. Graham said additional HMC Consortium members would be announced later this year. "We fully expect that there will be additional developers comprised of OEMs and enablers who will essentially be guiding the development of this spec," Graham said. HMC relies on through-silicon-vias (TSVs)for three-dimensional stacked layers of memory with interconnect that increases performance and lowers power consumption. It also incorporates a logic layer that allows for multiple configurations for scalable bandwidth and the design flexibility for HMC to be implemented on multiple platforms, across many applications, according to Micron and Samsung. The technology also promises wide, high-speed local buses for data movement, advanced memory controller functions, DRAM control at memory, reduced memory controller complexity and increased efficiency, according to the companies. In February, Micron introduced HMC's ability to integrate DRAM and logic processes together in one package. The current HMC platform—demonstrated last month—has validated that it can run at 128 FB/s, providing significant bandwidth, density and energy efficiency improvements, according to Micron. Micron and Samsung believe that HMC has the potential to deliver significant improvements for applications ranging from networking and data center to consumer products such as media tablets and cards. HMC also represents a fundamental shift from current memory architectures, and driving its integration and adoption as an open standard will be a major undertaking, the companies said. Graham said the companies believe that HMC will have the greatest near-term impact in areas where performance and energy efficiency are most critical, such as networking and high-performance computing. But ultimately the companies believe the technology will be adopted into a wide-variety of wireless, medical, energy, transportation and security devices, he said. Graham described HMC as a response to significant challenges facing traditional DRAM, including the so-called "memory wall" created by the inability of DRAM vendors to march the performance improvements of processors. As a result, memory has become a significant bottleneck for system performance, he said. "The CPUs are capable of processing a lot more information than the DRAM is able to deliver," said Pablo Temprano, director of DRAM marketing at Samsung Semiconductor. In response to the disparity between the speed of processors and memory, engineers introduced a hierarchy of cache memory that is capable of running at processor clock speeds, according to Graham. But with the advent of multi-core, multi-threaded processors, the memory needs of computational algorithms sometimes exceed the capacity of the processor cache, he said. HMC offers the potential to alleviate this bottleneck, according to Graham and Temprano. A single HMC unit can provide more than 15 times the bandwidth of a DDR3 module and offer significant improvement in response to a random request stream, reducing system latency, they said.