聯(lián)電(UMC)稍早前宣布，與 IBM 達成協(xié)議，將加快其 20nm 制程及 FinFET 3D 晶體管的發(fā)展，而此舉也很可能讓聯(lián)電成為唯一一家在 20nm 節(jié)點提供 FinFET 組件的純晶圓代工廠。 聯(lián)電正在努力扭轉局面。近年來，聯(lián)電和主要競爭對手臺積電(TSMC)的技術差距不斷拉大，而Globalfoundries不久前也宣布銷售額超越聯(lián)電，將聯(lián)電擠到了晶圓代工排名第三位。 臺積電 (TSMC) 和 Globalfoundries 都可算在2014或2015年時，于 14nm 節(jié)點導入3D FinFET組件。部份先進代工客戶如 Nvidia 則表示，他們希望代工廠能更快提供FinFET。因而部份業(yè)界人士猜測，臺積電和GlobalFoundries很可能會改變他們的發(fā)展藍圖，提前納入 FinFET。 Globalfoundries 發(fā)言人表示，該公司已經完成了完全耗盡型絕緣層上覆硅(SOI)技術的評估，預計2013年便可提供給客戶使用，而早期采用的客戶將可獲得該技術提供的性 能優(yōu)勢?！拔覀兒皖I先客戶密切合作，以確保這項技術在成本、易于設計、微縮等方面都是最佳化的解決方案?！? 英特爾 (Intel)已開始在22nm節(jié)點量產采用其FinFET組件(或稱三閘極晶體管, tri-gate)的芯片。目前，許多領先的無晶圓廠公司們，都希望藉由該技術來改善功耗。(英特爾已公開表示該公司正在為少數(shù)幾家規(guī)模較小的公司使用其 22nm 3D技術生產芯片。但也有傳言指出，英特爾也正與其它數(shù)家公司就代工業(yè)務展開合作，其中還包括一些重量級的無晶圓廠芯片業(yè)者)。 在 20nm節(jié)點納入FinFET將使聯(lián)電在標準平面20nm制外，也有能力提供20nm制程的低功耗版本。無論是臺積電或Globalfoundries， 都計劃提供低功耗20nm制程。今年四月，臺積電執(zhí)行副總暨共同營運長蔣尚義曾表示，20nm的關鍵尺寸幾乎沒有足夠空間來為不同閘極長度調整設計規(guī)則， 并提供不同版本的20nm制程了。 如果聯(lián)電能及時提供 20nm FinFET 低功耗制程，就能與對手做出重大區(qū)隔。而這或許也是該公司奪回近年來不斷被競爭對手所搶占市場的關鍵所在。 每個人都知道，功耗是芯片制造商和電子產業(yè)中幾乎每個人都最關心的議題。若聯(lián)電能在競爭對手都還沒準備好時，就提供低功耗20nm FinFET制程，這對業(yè)界會是多么大的震撼？ 英特爾負責制程技術研發(fā)的資深院士Mark Bohr對今年四月《EE Times》報導臺積電表示或許不打算提供低功耗20nm制程的報導所做出的反應，是認為芯片代工模式即將“崩潰”。Bohr的看法可能過于偏激了。但他 的出發(fā)點在于像美國高通這類無晶圓廠芯片業(yè)者，都會需要能盡可能降低芯片供耗的制程。 當然，目前有關聯(lián)電的20nm FinFET仍然只是一個計劃。即使獲得IBM的技術，卻也無法保證新制程的開發(fā)會一帆風順。而聯(lián)電本身也尚未對客戶提供任何有關該技術的時間表。 然而，若一切依計劃進行，則此舉將大幅強化聯(lián)電在代工領域的競爭力。 編譯： Joy Teng 本文授權編譯自EE Times，版權所有，謝絕轉載 本文下一頁：參考英文原文：UMC looks for boost with IBM license deal ，by Dylan McGrath

相關閱讀：
• 高通選擇代工伙伴的糾結之心
• 無晶圓廠經營模式在14nm的雞血下仍將堅挺
• 聯(lián)電南科廠動土，2013下半年裝機aO7esmc

{pagination} UMC looks for boost with IBM license deal Dylan McGrath United Microelectronics Corp.'s announcement Friday (June 29) that it has licensed from IBM technology to expedite the development of its 20-nm process, including FinFET transistors, likely means that UMC will be the only pure-play foundry to offer FinFETs at the 20-nm node. The effort appears to be an attempt by UMC to stem the tide of recent years. Rival Taiwan Semiconductor Manufacturing Co. (TSMC) has widened the technology gap with UMC as of late, and Globalfoundries Inc. recently surpassed UMC to claim the No. 2 position in foundry sales. Both TSMC and Globalfoundries are currently planning to introduce FinFETs—three-dimensional, fin-based multi-gate transistors—at the 14-nm node in 2014 or 2015. Some advanced foundry customers, including Nvidia Corp., have said they would like the foundries to offer FinFETs earlier. There is some speculation that TSMC and Globalfoundries may alter their roadmaps to incorporate FinFETs earlier. A spokesman for Globalfoundries said Friday that the company has been evaluating a fully depleted silicon-on-insulator technology offering in 2013 for early-adopter customers who may benefit from an additional performance boost. "We are in close discussion with leading customers to make sure this technology is the most optimum solution in terms of cost, ease of design, scaling and risk," the spokesman said. Intel Corp. is already producing chips with FinFETs—or what Intel calls tri-gate transistors—at the 22-nm node. Leading-edge fabless firms want the power consumption improvement promised by the technology. (Intel has publicly disclosed that it is making chips for a handful of smaller companies using its 22-nm 3-D process. Rumor has it that it is working on a foundry basis for several other companies, as well, including some fairly sizeable fabless chip vendors). The incorporation of FinFETs at 20-nm will enable UMC to offer a low-power version of its 20-nm process, in addition to a standard planar 20-nm process. Neither TSMC or Globalfoundries is planning to have a low-power 20-nm process. In April, Shang-yi Chiang, executive vice president and co-chief operating officer at TSMC, said critical dimensions are so tight at 20-nm that there isn't enough room for tweaking design rules to specify different gate lengths to enable different flavors of 20-nm processes. If UMC is able to offer a 20-nm low-power process with FinFETs in a timely fashion, it could be a major differentiator. It could be just what the company needs to recapture some of the ground it has given up to competitors in recent years. Everyone understands that power consumption is an issue of paramount concern to chip makers and just about everyone else in electronics today. How big of a deal will it be if UMC can offer a low-power 20-nm process with FinFETs at a time when competitors do not? Mark Bohr, the Senior Fellow at Intel who oversees the company's process technology development, reacted to the news that TSMC would not offer a low-power process at 20-nm by declaring to EE Times in April that the foundry model was "collapsing." Bohr's comments were self-serving and likely a little over the top. But his central point, that fabless chip vendors like Qualcomm Inc. need a process that will make its chips consume as little power as possible, has some merit. Of course, it should be said here that UMC's plan to offer FinFETs at 20-nm is, at this point, just a plan. Even with the IBM technology, there is no guarantee that devleoping the new process will go out without a hitch. And UMC itself has offered no timetable for when this technology will be available to customers. But if all goes according to plan, the move could well be enough to put UMC back in a place of greater relevance to leading edge foundry customers.