在Semicon Taiwan半導(dǎo)體設(shè)備展上，晶圓代工大廠臺(tái)積電(TSMC)的高層指出，要趕上 14奈米節(jié)點(diǎn)芯片在2015年的量產(chǎn)時(shí)程，時(shí)間已經(jīng)不多了，但設(shè)備業(yè)者卻動(dòng)作太慢。臺(tái)積電認(rèn)為，要讓 14奈米芯片達(dá)到成本效益，需要采用下一代微影技術(shù)以及 18寸晶圓，但設(shè)備業(yè)者在這兩方面都沒(méi)有趕上晶圓代工業(yè)者的時(shí)間表。 臺(tái)積電研發(fā)資深副總蔣尚義(Shang-Yi Chiang)表示：“我們一天比一天更擔(dān)心?！本A廠的產(chǎn)能需要達(dá)到每小時(shí)100片以上晶圓片，但到目前為止，超紫外光(EUV)微影技術(shù)產(chǎn)量最多僅能達(dá)到每小時(shí)5片晶圓；其它兩種采用多重電子束直寫方案的備選微影技術(shù)，一小時(shí)的產(chǎn)量甚至不到1片晶圓。 “臺(tái)積電在幾個(gè)月之前就提出了我們的 18寸晶圓愿望清單，但有部分設(shè)備業(yè)者認(rèn)為那太趕了，所以現(xiàn)在我們也不知道確切的時(shí)間表將會(huì)如何；”蔣尚義接受EETimes編輯訪問(wèn)時(shí)指出：“我們可能得采取轉(zhuǎn)換至0.13微米制程時(shí)的做法，當(dāng)時(shí)有部分產(chǎn)能是采用8寸晶圓，有部分是采用12寸晶圓?！? 臺(tái)積電目前計(jì)劃在新竹的Fab 12建置一條18寸晶圓試產(chǎn)線，然后在臺(tái)中設(shè)置量產(chǎn)線；更大尺寸的晶圓片將有助于半導(dǎo)體產(chǎn)業(yè)趕上摩爾定律(Moore's Law)的腳步，并將IC制造成本降低至少30%。18寸晶圓可讓代工業(yè)者減少晶圓廠數(shù)量，并因此節(jié)省大量的土地與人力成本。 舉例來(lái)說(shuō)，為了達(dá)到3,200萬(wàn)片8寸約當(dāng)晶圓的產(chǎn)能需求，若以現(xiàn)在的12寸晶圓進(jìn)行生產(chǎn)，臺(tái)積電得雇用2萬(wàn)7,000名工程師維持29座廠房營(yíng)運(yùn)，但如果采用18寸晶圓，只需要2萬(wàn)名工程師、22座廠房?！?8寸晶圓不是一個(gè)技術(shù)議題，而是一個(gè)在這些日子以來(lái)比技術(shù)更重要的經(jīng)濟(jì)議題?！笔Y尚義表示。

18寸晶圓可讓業(yè)者節(jié)省土地與人力成本ePBesmc

在微影技術(shù)方面，目前的193奈米浸潤(rùn)式微影系統(tǒng)將使用于臺(tái)積電目前正在量產(chǎn)的28奈米節(jié)點(diǎn)，以及下一代的20奈米節(jié)點(diǎn)制程；但在20奈米節(jié)點(diǎn)部分，晶圓廠會(huì)需要用到雙重圖形(double patterning)方案，基本上就是讓晶圓片透過(guò)某種程序曝光兩次，以畫上更細(xì)的線條。 而到了14nm節(jié)點(diǎn)，以浸潤(rùn)式微影設(shè)備做雙重圖形，對(duì)許多客戶來(lái)說(shuō)價(jià)格會(huì)變得非常高，所以臺(tái)積電將在兩周內(nèi)開始測(cè)試ASML的3100系列EUV微影設(shè)備原型機(jī)；該公司已經(jīng)開始測(cè)試Mapper Lithography的電子束微影設(shè)備，并計(jì)劃在明年裝設(shè)另一臺(tái)由KLA Tencor提供的電子束微影設(shè)備。 “如果我們無(wú)法讓EUV或電子束微影設(shè)備，達(dá)到每小時(shí)100片晶圓的產(chǎn)量，我們可能會(huì)看到很少有客戶愿意繼續(xù)邁向更精細(xì)的制程技術(shù)節(jié)點(diǎn)，因?yàn)槌杀緦?shí)在太高?！笔Y尚義表示，臺(tái)積電計(jì)劃在2015年量產(chǎn)14nm節(jié)點(diǎn)制程，所以：“我們必須在明年決定要用哪一種微影設(shè)備。如果我們繼續(xù)專注于采用193奈米浸潤(rùn)式微影，稍后要轉(zhuǎn)換至EUV會(huì)變得很困難，而且設(shè)計(jì)規(guī)則必須要根據(jù)所選擇的微影技術(shù)來(lái)定義，所以時(shí)間真的很趕?！?

14奈米制程節(jié)點(diǎn)所需的微影技術(shù)成本飆高ePBesmc

蔣尚義表示，浸潤(rùn)式微影技術(shù)在14奈米節(jié)點(diǎn)會(huì)變得非常昂貴，顛覆以往每升級(jí)一個(gè)節(jié)點(diǎn)、資本設(shè)備支出會(huì)減半的原則；而雖然EUV與電子束微影設(shè)備的成本也很高，估計(jì)至少需要1.2億美元，但還是會(huì)比以浸潤(rùn)式微影技術(shù)進(jìn)行雙重圖形來(lái)得便宜許多。他并指出，電子束與EUV設(shè)備的價(jià)格差不多，但目前正在進(jìn)行測(cè)試的電子束微影設(shè)備不需要光罩，所以成本會(huì)比EUV微影技術(shù)稍低一些。 編譯：Judith Cheng 本文授權(quán)編譯自EE Times，版權(quán)所有，謝絕轉(zhuǎn)載 參考英文原文： TSMC says equipment vendors late for 14 nm，by Rick Merritt

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{pagination} TSMC says equipment vendors late for 14 nm Rick Merritt TAIPEI – Time is running out to make critical decisions for how to make 14-nm chips expected to hit production in 2015, and capital equipment vendors are falling behind. That was the upshot of a talk by the top R&D executive at Taiwan Semiconductor Manufacturing Co. (TSMC) at Semicon Taiwan here. TSMC believes it needs to move to next-generation lithography and 450-mm wafers to make 14-nm chips cost effectively, but capital equipment makers threaten to miss the foundry's schedule on both fronts. "Every day we become more and more concerned," said Shang-Yi Chiang, senior vice president of R&D of TSMC. Fabs need throughput of more than 100 wafers per hour. But so far extreme ultraviolet (EUV) lithography offers just five wafers per hour at best. Two alternatives using multiple e-beam direct write approaches get less than one. Similarly, TSMC "put out our wish list for 450-mm wafers a few months ago, but some in the capital equipment industry felt it was too aggressive so now we don’t know" what the schedule will be, Chiang said to EE Times after his talk. "We may have to do what we did at the 130-nm generation when some capacity was on 200- and some on 300-mm wafers," he said. TSMC currently plans to bring up a pilot 450-mm wafer line at its Fab 12 in Hsinchu, followed by a production line in Taichung. The larger wafers are needed both to help keep pace with Moore's Law and to lower wafer costs as much as 30 percent. The 450-nm wafers enable foundries to use fewer fabs, saving significant money on both land and labor costs. To meet expected demand for 32 million eight-inch equivalent wafers, TSMC could hire 20,000 engineers to run 22 plants. If it has to use today's 300-mm wafers the same output would require 29 plants and 27,000 engineers, Chiang estimated. "450-mm wafers are not a technical issue but an economic issue which is probably more important than technical issue these days," Chiang said. In lithography, today's 193-nm immersion systems will serve both the 28-nm node TSMC is ramping now and the next-generation 20-nm node. But at 20 nm, fabs will need to use double patterning, essentially running wafers through some exposure processes twice to draw finer lines. At 14 nm the amount of double patterning with immersion systems could become prohibitively expensive for many customers. So TSMC will start testing a prototype 3100 series EUV machine from ASML in two weeks. It has already been testing an e-beam system from Mapper Lithography BV and will install another from KLA Tencor next year. "If we cannot get EUV or e-beam to 100 wafers per hour throughput, we see few customers will be willing to continue migrating to finer technology nodes because of the cost," he warned. TSMC hopes to ramp a 14-nm process in 2015 so "we have to make this decision [on lithography] early next year," Chiang said. "If we focus on using 193-nm immersion it becomes difficult to switch to EUV later on, [and] design rules will be defined based on the choice of lithography, so time is running out," he said. New transistors needed at 14nm Chiang suggested immersion lithography would be too expensive at 14 nm, exceeding traditional guidelines of half the capital equipment costs for a node. Despite the enormous costs of EUV and e-beam machines, estimated at as much as $120 million, they are still cheaper than immersion given the double patterning problems. E-beam and EUV systems cost roughly the same. But E-beam systems currently under test do not require masks so could slightly cheaper to use than EUV, Chiang said. EUV has "the broadest support and is the most likely route" forward, said Luc Van den hove, chief executive of the Imec research consortium based outside Brussels. "But this year and next we have to demo the production worthiness of this technology," Van den hove said in a separate talk. Imec has been running wafers through an ASML 3100 pre-production system for three months "and we've seen improvement in throughput, but progress has been too slow and we have to further accelerate it," he said. The power of the EUV source light is still too low, despite defining two approaches to creating the light source. "Progress has not been sufficient, and this is one of the highest priorities," said Van den hove who once ran Imec's lithography program. As if the capital equipment problems were not enough, TSMC expects it will need to transition to a new transistor design at 14 nm, likely a FinFET. Intel announced plans to use such a 3-D transistor design starting at 20 nm. Both TSMC and GlobalFoundries believe planar transistors can be used down to 20 nm. But they both expect to make the switch to 3-D structures such as FinFETs or fully depleted SOI at 14 nm. Van den hove said FinFETs "are probably the most likely way. Beyond that we believe another technology breakthrough will be needed likely using super-high mobility materials such as germanium p-channel and III-IV materials for n-channels for 10 nm nodes," he added. The good news is unexpected innovations have powered the industry past roadblocks in previous generations, despite as many as ten past predictions that Moore's law would end, said Chiang of TSMC. Based on feasibility demonstrations, he projected currently defined technologies could take CMOS scaling to geometries as fine as 7 nm.