在本周于美國舉行、聚集眾多頂尖微處理器架構(gòu)師的年度 Hot Chips 大會(huì)上，發(fā)表多場(chǎng)演說的ARM是聚光燈焦點(diǎn)之一，但顯然英特爾(Intel)仍是微處理器領(lǐng)域的霸主。IBM與甲骨文(Oracle)也藉由大會(huì)上的演說展示其Power 8與Sparc架構(gòu)仍在市場(chǎng)上各自占有一席之地，而這兩家公司表示，芯片堆棧方案正在崛起。 值 得一提的是，在這為期三天的Hot Chips大會(huì)上，筆者完全沒聽到有人提“CPU”這個(gè)縮寫，看來它已經(jīng)是過氣的名詞。主流28納米制程技術(shù)的問世──以及少數(shù)以更具侵略性制程節(jié)點(diǎn)生產(chǎn) 的芯片──顯然已經(jīng)讓微處理器演進(jìn)至系統(tǒng)級(jí)芯片(SoC)時(shí)代?？赡苓@樣的歷史趨勢(shì)正是 ARM 在大會(huì)上備受矚目的原因；x86或許仍是重量級(jí)架構(gòu)，但ARM核心則是會(huì)出現(xiàn)在大多數(shù)工程師的設(shè)計(jì)中。以下是 2014年度的Hot Chips大會(huì)重點(diǎn)摘錄。 ARM在物聯(lián)網(wǎng)世界試水溫 ARM首席技術(shù)官M(fèi)ike Muller介紹了一款嵌入了傳感器中樞(sensor hub)、鎖定物聯(lián)網(wǎng)(IoT)應(yīng)用的測(cè)試芯片；Muller表示他上一次在Hot Chips大會(huì)介紹ARM技術(shù)得回溯到1992年。

ARM介紹內(nèi)嵌傳感器中樞的物聯(lián)網(wǎng)芯片
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此外，Muller也呼吁工程師們參與將接棒今日DDR4規(guī)格的Jedec 內(nèi)存新標(biāo)準(zhǔn)訂定。

目前市面上的解決方案大多采用離散式的傳感器中樞芯片
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本文授權(quán)編譯自EE Times，版權(quán)所有，謝絕轉(zhuǎn)載 本文下一頁：AMD首款A(yù)RM架構(gòu)服務(wù)器SoC——“西雅圖”亮相 {pagination} AMD的ARM架構(gòu)服務(wù)器SoC亮相 AMD 在大會(huì)上介紹第一款采用ARM架構(gòu)的服務(wù)器SoC，代號(hào)Seattle；這款芯片預(yù)定在今年底前量產(chǎn)。Insight64分析師Nathan Brookwood表示，該款芯片采用標(biāo)準(zhǔn)ARM 64位核心，可能會(huì)吸引對(duì)一些采用客制化核心之競(jìng)爭產(chǎn)品兼容性有疑慮的客戶。

AMD的Seattle服務(wù)器SoC架構(gòu)
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如同眾多服務(wù)器SoC，內(nèi)存在Seattle芯片內(nèi)扮演主要角色
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本文授權(quán)編譯自EE Times，版權(quán)所有，謝絕轉(zhuǎn)載 本文下一頁：Applied Micro展示X-Gene產(chǎn)品藍(lán)圖 {pagination} Applied Micro展示X-Gene產(chǎn)品藍(lán)圖 Applied Micro的40納米X-Gene系列ARM核心64位服務(wù)器SoC已經(jīng)量產(chǎn)，該公司在大會(huì)上介紹的是還在開發(fā)階段的第二代X-Gene，以及計(jì)劃才剛成形的第三代。

Applied Micro展示X-Gene 產(chǎn)品藍(lán)圖
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如同AMD的Seattle，Applied Micro介紹其第二代X-Gene芯片將配備8顆64位ARM 核心，初估該芯片性能將比第一代高出30~100%。

Applied Micro的第二代X-Gene芯片架構(gòu)
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第二代X-Gene芯片性能與前一代產(chǎn)品之比較
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本文授權(quán)編譯自EE Times，版權(quán)所有，謝絕轉(zhuǎn)載 本文下一頁：英特爾Avoton定位低功耗服務(wù)器等級(jí)SoC {pagination} 英特爾Avoton要求低功耗 處理器龍頭英特爾在大會(huì)上介紹了第二代Atom核心服務(wù)器SoC，代號(hào)Avoton；該芯片試圖與ARM架構(gòu)服務(wù)器芯片一較高下，自定位為低功耗的服務(wù)器等級(jí)SoC。

英特爾介紹低功耗Atom核心服務(wù)器芯片Avoton
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英特爾表示Atom架構(gòu)芯片已經(jīng)獲得眾多客戶采用
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本文授權(quán)編譯自EE Times，版權(quán)所有，謝絕轉(zhuǎn)載 本文下一頁：英偉達(dá)“丹佛”芯片仍將鎖定移動(dòng)設(shè)備應(yīng)用 {pagination} Nvidia的Denver芯片仍將鎖定移動(dòng)設(shè)備應(yīng)用 Nvidia的客制化64位ARM核心芯片Denver，是以行動(dòng)SoC的身分首度亮相；據(jù)業(yè)界消息，該公司已經(jīng)取消了進(jìn)軍服務(wù)器應(yīng)用的計(jì)劃，但對(duì)此該公司不愿評(píng)論。

Nvidia介紹64位行動(dòng)處理器Denver
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據(jù)了解，Denver原本將采用收購自Transmeta 的技術(shù)、為x86架構(gòu)芯片，后來卻演變成采用了一種新式執(zhí)行優(yōu)化功能，取代其他競(jìng)爭對(duì)手所采用的全亂序執(zhí)行(full out-of-order)設(shè)計(jì)(參考閱讀《揭密英偉達(dá)客制化64位ARM核心處理器》)。

Nvidia的Denver芯片支持執(zhí)行優(yōu)化功能
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本文授權(quán)編譯自EE Times，版權(quán)所有，謝絕轉(zhuǎn)載 本文下一頁：已經(jīng)收歸英特爾旗下的安華高網(wǎng)絡(luò)處理器Axxia {pagination} 已經(jīng)收歸英特爾旗下的Avago網(wǎng)絡(luò)處理器Axxia 安華高(Avago)在Hotchips大會(huì)上介紹收購自LSI的ARM核心網(wǎng)絡(luò)處理器Axxia，但在那之后過兩天，該芯片就已經(jīng)賣給英特爾；據(jù)分析師表示，英特爾將會(huì)利用從英飛凌(Infineon)收購的手機(jī)應(yīng)用處理器技術(shù)，以x86架構(gòu)設(shè)計(jì)下一代的Axxia芯片。

Axxia網(wǎng)絡(luò)處理器架構(gòu)
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本文授權(quán)編譯自EE Times，版權(quán)所有，謝絕轉(zhuǎn)載 本文下一頁：IBM為Power 8打造新軟件 {pagination} IBM為Power 8打造新軟件 IBM在去年的Hot Chips大會(huì)發(fā)表Power 8處理器，今年則是為該款芯片開發(fā)了新的軟件堆棧；Power架構(gòu)是開放給所有芯片與系統(tǒng)開發(fā)商的資源，IBM改寫了其軟件堆棧，包括新版本的Linux、新的hypervisor、新的韌體等等。

IBM為Power 8打造新軟件
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Power 8首度登場(chǎng)時(shí)被譽(yù)為最具擴(kuò)充性的服務(wù)器處理器
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本文授權(quán)編譯自EE Times，版權(quán)所有，謝絕轉(zhuǎn)載 本文下一頁：甲骨文介紹32核心Sparc處理器 {pagination} 甲骨文介紹32核心Sparc處理器 甲骨文在大會(huì)上介紹其迄今最大規(guī)模的Sparc處理器芯片M7，內(nèi)含32顆多執(zhí)行續(xù)(multithreaded)核心，可擴(kuò)充為32路、8,000執(zhí)行續(xù)的系統(tǒng)。市場(chǎng)研究機(jī)構(gòu)Brookwood的分析師形容，M7的內(nèi)存層級(jí)、互連以及高速緩存容量之可擴(kuò)充性令人驚艷，是一款“大氣”的芯片。

甲骨文32核心Spac處理器M7
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M7 是為甲骨文的軟件堆棧量身打造，Tirias Research分析師Kevin Krewell表示，其功能包括Java垃圾回收加速(garbage collection acceleration)，以及一款甲骨文數(shù)據(jù)庫查詢加速器(query accelerator)。

M7處理器性能一覽
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本文授權(quán)編譯自EE Times，版權(quán)所有，謝絕轉(zhuǎn)載 本文下一頁：AMD公開CPU/GPU組合芯片Kaveri細(xì)節(jié) {pagination} AMD公開CPU/GPU組合芯片Kaveri細(xì)節(jié) AMD 也在大會(huì)上公開了客戶端運(yùn)算CPU/GPU組合芯片Kaveri的細(xì)節(jié)，這款芯片在去年首度亮相，值得一探究竟的原因是，該芯片采用AMD的異質(zhì)系統(tǒng)架構(gòu) (Heterogeneous Systems Architecture，HSA)是首款支持連貫性連結(jié)(coherent connection)，以及CPU與GPU之間的完全內(nèi)存共享。現(xiàn)在的疑問是誰將采用第二代HSA芯片？何時(shí)有產(chǎn)品上市？

CPU/GPU組合芯片Kaveri架構(gòu)
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Kaveri采用AMD的異質(zhì)系統(tǒng)架構(gòu)
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本文授權(quán)編譯自EE Times，版權(quán)所有，謝絕轉(zhuǎn)載 本文下一頁：SK海力士介紹自家芯片堆棧方案 {pagination} SK海力士介紹自家芯片堆棧方案 Xilinx率先以2.5D芯片堆棧將內(nèi)存與FPGA并排放置在一片基板上，SK海力士(Hynix)則表示那只是開始，接下來將是繪圖處理器芯片、網(wǎng)絡(luò)芯片堆棧…有一天也許能迭出一支智能手機(jī)所需的各種功能。

SK海力士介紹其芯片堆棧方案
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SK海力士也詳細(xì)介紹了其高帶寬內(nèi)存(High Bandwidth Memory)的進(jìn)展。

SK海力士的高帶寬內(nèi)存
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本文授權(quán)編譯自EE Times，版權(quán)所有，謝絕轉(zhuǎn)載 本文下一頁：創(chuàng)新芯片無線堆棧技術(shù) {pagination} 創(chuàng)新芯片無線堆棧技術(shù) 微處理器領(lǐng)域的資深工程師Dave Ditzel表示，新創(chuàng)公司ThruChip Communications開發(fā)出一種能跨越芯片無線分配電力的方法，這種技術(shù)與該公司在芯片之間傳遞數(shù)據(jù)的電感耦合技術(shù)結(jié)合，可做為取代昂貴且復(fù)雜之硅穿孔技術(shù)的替代方案。

ThruChip Communications開發(fā)的芯片無線堆棧技術(shù)架構(gòu)
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該種耦合技術(shù)甚至看起來更適合目前新開發(fā)的超薄晶圓技術(shù)，因?yàn)楸⌒酒蛇m合更小的感應(yīng)線圈。

新開發(fā)的超薄晶圓技術(shù)
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本文授權(quán)編譯自EE Times，版權(quán)所有，謝絕轉(zhuǎn)載 本文下一頁：微軟和百度都打算用FPGA來加速數(shù)據(jù)中心 {pagination} 其他熱門話題 在今年Hot Chips大會(huì)上最熱門的、運(yùn)算領(lǐng)域以外的話題，一個(gè)是微軟(Microsoft)打算采用Altera的FPGA來加速其數(shù)據(jù)中心的Bing服務(wù)，為可程序化邏輯組件開啟了新應(yīng)用；而百度(Baidu)也表示將支持這樣的轉(zhuǎn)變。

微軟數(shù)據(jù)中心將利用Altera FPGA加速Bing服務(wù)
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此外有一家比特幣采礦機(jī)(bitcoin mining)新創(chuàng)公司，采用高程度的設(shè)計(jì)重復(fù)使用方法，在不到一年時(shí)間內(nèi)讓整體系統(tǒng)速度破紀(jì)錄。

重復(fù)使用設(shè)計(jì)方案協(xié)助業(yè)者大幅提升系統(tǒng)性能
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本文授權(quán)編譯自EE Times，版權(quán)所有，謝絕轉(zhuǎn)載 編譯：Judith Cheng 參考英文原文：25 Views of Hot Chips 2014，by Rick Merritt {pagination} 25 Views of Hot Chips 2014 Rick Merritt CUPERTINO, Calif. — ARM commanded much of the spotlight with a half-dozen presentations at Hot Chips, an annual gathering of top microprocessor architects. But the event made it clear Intel is still king of the silicon hill. IBM and Oracle gave talks showing their Power 8 and Sparc architectures are still very much in the game. And two talks showed that chip stacks are on the rise. One acronym I never heard uttered during the three-day event was CPU, a term that has become so last century. The advent of mainstream 28nm process technology -- and a handful of chips built on more aggressive nodes – has clearly morphed the microprocessor into the SoC era. Perhaps this historical trend is why ARM figured so prominently in the proceedings. The x86 may still be the 900-pound gorilla, but the ARM core is the one available for most engineer’s designs. ARM tests IoT ARM's CTO Mike Muller described a test chip for the Internet of Things that embedded a sensor hub (below), a separate chip in some of today's products. Muller noted back in 1992 he gave the sole ARM paper at Hot Chips. Fast forward to 2014 and his talk was one of six on ARM chips. ARM's CTO Mike Muller described a test chip for the Internet of Things that embedded a sensor hub (below), a separate chip in some of today's products. Muller noted back in 1992 he gave the sole ARM paper at Hot Chips. Fast forward to 2014 and his talk was one of six on ARM chips. Separately, Muller also called for engineers to get involved in a new Jedec memory standard that will be a follow on to today's DDR4 spec. Separately, Muller also called for engineers to get involved in a new Jedec memory standard that will be a follow on to today's DDR4 spec. AMD tours Seattle AMD described Seattle, its first ARM-based server SoC. It aims to have it in production before the end of the year. Use of a standard ARM 64-bit core may attract buyers concerned about possible incompatibility issues with custom cores some competitors are designing, said analyst Nathan Brookwood of Insight64. AMD described Seattle, its first ARM-based server SoC. It aims to have it in production before the end of the year. Use of a standard ARM 64-bit core may attract buyers concerned about possible incompatibility issues with custom cores some competitors are designing, said analyst Nathan Brookwood of Insight64. As is the case with many server SoCs, memory dominates the Seattle die. Applied Micro shows XGene road map Applied Micro said it has production volumes of its 40nm X-Gene, one of the first 64-bit ARM-based server SoCs to hit the market. It detailed its second-generation now in the lab and sketched out rough plans for a third generation. Applied Micro said it has production volumes of its 40nm X-Gene, one of the first 64-bit ARM-based server SoCs to hit the market. It detailed its second-generation now in the lab and sketched out rough plans for a third generation. Like AMD's Seattle, Applied's Shadowcat, its second-generation X-Gene will sport eight 64-bit ARM cores(see above). Initial performance figures show the chip offering a 30-100% performance boost over the first-gen part (see below). Like AMD's Seattle, Applied's Shadowcat, its second-generation X-Gene will sport eight 64-bit ARM cores(see above). Initial performance figures show the chip offering a 30-100% performance boost over the first-gen part (see below). Intel rules the microserver Intel described Avoton, its second-generation Atom-based server SoC, intended to stave off competition from ARM-based servers. As it turned out competitors have hardly made it to market. Meanwhile Intel grabbed the early sockets for low-power server-class SoCs (see below). Intel described Avoton, its second-generation Atom-based server SoC, intended to stave off competition from ARM-based servers. As it turned out competitors have hardly made it to market. Meanwhile Intel grabbed the early sockets for low-power server-class SoCs (see below). Nvidia's Denver stays mobile Denver, Nvidia's custom 64-bit ARM core, made its debut in a mobile SoC. Reports say Nvidia cancelled its plans for a server part, but the company declined comment. Denver, Nvidia's custom 64-bit ARM core, made its debut in a mobile SoC. Reports say Nvidia cancelled its plans for a server part, but the company declined comment. Initially, Denver was going to be an x86 chip, reportedly using technology from Transmeta. But it morphed instead into an ARM chip using a novel optimizer as an alternative to doing a full out-of-order design like its server SoC competitors Applied Micro, Broadcom and Cavium. It may take until some time in 2015 befor benchmarks with all the chips determine which route was best for performance/Watt. Initially, Denver was going to be an x86 chip, reportedly using technology from Transmeta. But it morphed instead into an ARM chip using a novel optimizer as an alternative to doing a full out-of-order design like its server SoC competitors Applied Micro, Broadcom and Cavium. It may take until some time in 2015 befor benchmarks with all the chips determine which route was best for performance/Watt. Intel grabs Avago's Axxia Avago described Axxia, the ARM-based networking SoC it acquired with LSI. Two days later it sold the chip to Intel which is expected to design a next-generation part based on the x86, the approach Intel took with the mobile application processor it acquired with Infineon, noted analyst Brookwood. Avago described Axxia, the ARM-based networking SoC it acquired with LSI. Two days later it sold the chip to Intel which is expected to design a next-generation part based on the x86, the approach Intel took with the mobile application processor it acquired with Infineon, noted analyst Brookwood. Power 8 revamps software The big news about IBM's Power 8, disclosed at last year's event, was a new software stack (see above). In an effort to make Power open to any chip or system developer, IBM re-wrote its software stack including a new version of Linux, a new hypervisor, new firmware, and other goodies. The big news about IBM's Power 8, disclosed at last year's event, was a new software stack (see above). In an effort to make Power open to any chip or system developer, IBM re-wrote its software stack including a new version of Linux, a new hypervisor, new firmware, and other goodies. Power 8 was hailed as one of the most scalable server processors when it originally debuted. Oracle packs 32 Sparc cores Oracle disclosed its largest Sparc chip to date. The M7 packs 32 multithreaded cores and can expand into a 32-way system with 8,000 threads. 'I was blown away by the scalability of the M7 in the memory hierarchy, interconnect and cache sizes. This is a big ambitious chip,' said analyst Brookwood. Oracle disclosed its largest Sparc chip to date. The M7 packs 32 multithreaded cores and can expand into a 32-way system with 8,000 threads. "I was blown away by the scalability of the M7 in the memory hierarchy, interconnect and cache sizes. This is a big ambitious chip," said analyst Brookwood. The M7 is tailored for Oracle's software stack, sporting 'features such as Java garbage collection acceleration and an Oracle database query accelerator,' said analyst Kevin Krewell of Tirias Research. The M7 is tailored for Oracle's software stack, sporting "features such as Java garbage collection acceleration and an Oracle database query accelerator," said analyst Kevin Krewell of Tirias Research. AMD's coherant message AMD did a deep dive on Kaveri, its client computing CPU/GPU combo first described last year. It was worth a closer look because it's the first chip to support a coherent connection and full memory sharing between the CPU and GPU cores thanks to AMD's Heterogeneous Systems Architecture. Now the big question is, who will have the second HSA-compliant chip? And when? AMD did a deep dive on Kaveri, its client computing CPU/GPU combo first described last year. It was worth a closer look because it's the first chip to support a coherent connection and full memory sharing between the CPU and GPU cores thanks to AMD's Heterogeneous Systems Architecture. Now the big question is, who will have the second HSA-compliant chip? And when? Chip stacks get real Xilinx pioneered 2.5-D chip stacks putting memory and FPGA next to each other on a substrate. SK Hynix said that's just the start, with graphics apps coming next followed by networking chips...and someday maybe even the Holy Grail of smartphones. The company detailed the advantages of its High Bandwidth Memory offering (see below). Xilinx pioneered 2.5-D chip stacks putting memory and FPGA next to each other on a substrate. SK Hynix said that's just the start, with graphics apps coming next followed by networking chips...and someday maybe even the Holy Grail of smartphones. The company detailed the advantages of its High Bandwidth Memory offering (see below). Wireless chip stacks Startup ThruChip Communications has found a way to wirelessly distribute power across a chip, said microprocessor veteran Dave Ditzel. The technique (above) when combined with its inductive coupling method for passing data between chip die provides an alternative to expensive and complex through silicon vias, he said. The coupling technology is looking even better for those using the new ultra-thin wafers (see below) now emerging from the labs because the thin chips allow for smaller coils, he added. Startup ThruChip Communications has found a way to wirelessly distribute power across a chip, said microprocessor veteran Dave Ditzel. The technique (above) when combined with its inductive coupling method for passing data between chip die provides an alternative to expensive and complex through silicon vias, he said. The coupling technology is looking even better for those using the new ultra-thin wafers (see below) now emerging from the labs because the thin chips allow for smaller coils, he added. FPGAs, Bitcoin rising Two of the hottest Hot Chip talks came from outside the mainstream computing field the conference usually addresses. Microsoft's plan to adopt Altera FPGAs to accelerate Bing in its data centers opens a new door for programmable logic (above), a shift Baidu also said it supports. Separately, a bitcoin mining startup beat speed records getting full systems out the door in well less than a year (see below) thanks to a high degree of design re-use. Two of the hottest Hot Chip talks came from outside the mainstream computing field the conference usually addresses. Microsoft's plan to adopt Altera FPGAs to accelerate Bing in its data centers opens a new door for programmable logic (above), a shift Baidu also said it supports. Separately, a bitcoin mining startup beat speed records getting full systems out the door in well less than a year (see below) thanks to a high degree of design re-use.