至今全世界最像人腦的計(jì)算機(jī)芯片一直由IBM所主導(dǎo)開(kāi)發(fā)，該公司在Cornell Tech與iniLabs, Ltd等公司的攜手合作下，為美國(guó)國(guó)防部先進(jìn)研究計(jì)劃署(DARPA)的神經(jīng)形態(tài)自適應(yīng)塑料可微縮電子(SyNAPSE)系統(tǒng)計(jì)劃打造先進(jìn)的“類人腦芯片”。 這種半導(dǎo)體將來(lái)可能應(yīng)用于研發(fā)即使沒(méi)有人類命令也能自己學(xué)習(xí)，進(jìn)而解決問(wèn)題的人工智能。“當(dāng)我們?cè)诹昵皢?dòng) SyNAPSE 計(jì)劃時(shí)，很多人認(rèn)為不可能實(shí)現(xiàn)，”IBM院士兼IBM Research腦啟發(fā)運(yùn)算研究中心首席科學(xué)家Dharmendra Modha表示，“但是現(xiàn)在我們已經(jīng)證明它是可能的，而且我們正致力于使其于未來(lái)實(shí)現(xiàn)商業(yè)化?！毕嚓P(guān)內(nèi)容發(fā)表在8月8日的美國(guó)《科學(xué)》雜志上。 人類大腦的神經(jīng)細(xì)胞由無(wú)數(shù)被稱為“突觸(synapse)”的組織連接起來(lái)，能傳遞信息和進(jìn)行記憶。大腦盡管體積有限，但能夠以微量的能量完成復(fù)雜的工作。有分析認(rèn)為如果制成模擬大腦的半導(dǎo)體芯片，就能開(kāi)發(fā)出能完成人類大腦同樣工作的計(jì)算機(jī)。 IBM的SyNAPSE芯片擁有1百萬(wàn)個(gè)人工神經(jīng)元(類腦細(xì)胞)和2.56億個(gè)突觸(儲(chǔ)存單元)，以及4,096個(gè)稱為“神經(jīng)突觸”(neurosynaptic)的處理核心執(zhí)行作業(yè)，并整合內(nèi)存、運(yùn)算、通訊，以及以一種異步事件驅(qū)動(dòng)、平行與容錯(cuò)的方式作業(yè)。根據(jù)這種技術(shù)制造出的半導(dǎo)體從設(shè)計(jì)理念上就不同于現(xiàn)有計(jì)算機(jī)使用的半導(dǎo)體芯片。

IBM的neurosynaptic處理器在單一芯片上整合了1百萬(wàn)個(gè)神經(jīng)元以及2.56億個(gè)突觸。
Source：IBMfD7esmc

本文授權(quán)編譯自EE Times，版權(quán)所有，謝絕轉(zhuǎn)載 本文下一頁(yè)：比當(dāng)今微處理器所需功率低5000倍以上 {pagination} “這款處理器整合了54億個(gè)晶體管，可說(shuō)是IBM有史以來(lái)最大的芯片，而且，據(jù)我們所知是至今全世界最大型的芯片，但功耗僅70mW，”Modha說(shuō)。研究團(tuán)隊(duì)利用試制的半導(dǎo)體芯片，成功完成了對(duì)人物圖像等的識(shí)別工作。 為了衡量這一龐大的芯片的性能，IBM發(fā)明了一種新的度量標(biāo)準(zhǔn)——每秒突觸運(yùn)算(synaptic operations per second；SOPS)，以取代每秒浮點(diǎn)運(yùn)算(FLOPS)性能。 “該芯片可提供每瓦460億的SOPS，這款相當(dāng)于一張郵票大小的超級(jí)計(jì)算機(jī)重量卻輕如羽毛，所需的電源也僅約一款助聽(tīng)器的用量，”Modha說(shuō)，“它可作為監(jiān)控傳感器、移動(dòng)設(shè)備、執(zhí)行云端服務(wù)以及超級(jí)運(yùn)算的理想應(yīng)用。” 該架構(gòu)每平方公分消耗20mW功耗，比當(dāng)今微處理器所需的功率更低5,000倍以上。該芯片架構(gòu)基于先前在每個(gè)neurosynaptic核心中內(nèi)含256 個(gè)神經(jīng)元的上一代芯片。而在這款第二代芯片中，IBM不僅為其縮減了15倍的芯片面積、功耗降低100倍，同時(shí)還為每個(gè)芯片增加至4096個(gè)核心。 該 核心由芯片上網(wǎng)狀網(wǎng)絡(luò)以及相鄰芯片間直接鏈接的方式進(jìn)行連結(jié)。各芯片之間無(wú)縫地彼此連接，以期形成未來(lái)neurosynaptic超級(jí)計(jì)算機(jī)的基礎(chǔ)。此外， 為了證明其可擴(kuò)展性，IBM并展示了一款16芯片的系統(tǒng)，可將芯片架構(gòu)擴(kuò)展至1,600萬(wàn)個(gè)可編程的神經(jīng)元以及40億個(gè)可編程的突觸，其終極目標(biāo)在于達(dá)到 人腦神經(jīng)系統(tǒng)所需的100兆或更多個(gè)突觸。 “我們認(rèn)為，這款芯片為這款具有全新架構(gòu)、無(wú)與倫比的規(guī)模、速度、功效和可擴(kuò)展性的neurosynaptic計(jì)算機(jī)，建立了一個(gè)全新的里程碑，”Modha說(shuō)。

該芯片(左)布局是由64x64個(gè)神經(jīng)突觸核心數(shù)組組成，每個(gè)核心(右)內(nèi)含256顆神經(jīng)元以及65,536個(gè)突觸，以實(shí)現(xiàn)密集運(yùn)算、儲(chǔ)存與通訊。
Source：IBMfD7esmc

本文授權(quán)編譯自EE Times，版權(quán)所有，謝絕轉(zhuǎn)載 本文下一頁(yè)：“非諾伊曼型”的新一代半導(dǎo)體 {pagination} 被譽(yù)為“計(jì)算機(jī)之父”的數(shù)學(xué)家馮·諾伊曼（von Neumann）于1946年提出計(jì)算機(jī)構(gòu)想。之后的計(jì)算機(jī)都采取根據(jù)事先存儲(chǔ)的程序，逐步執(zhí)行命令的模式。這種計(jì)算機(jī)被稱為“諾伊曼型”。從設(shè)想提出直到如今，所有的計(jì)算機(jī)都采用了諾伊曼型。不過(guò)，對(duì)半導(dǎo)體進(jìn)行微細(xì)加工，以提升計(jì)算機(jī)處理速度這一傳統(tǒng)方式在加工技術(shù)方面正在趨近極限。 IBM 表示，經(jīng)由整合處理、儲(chǔ)存與通訊，目前已能消除令人生畏的“馮·諾伊曼”瓶頸––迫使傳統(tǒng)微處理器求助于多層次功耗快取。而且，由于所有的核心以平行方式執(zhí)行，不必再以GHz級(jí)的功耗作業(yè)。事實(shí)上，1kHz芯片 頻率可用于離散神經(jīng)元?jiǎng)討B(tài)。而藉由在整個(gè)芯片上平均分散核心，使該架構(gòu)具備容錯(cuò)能力；任何核心錯(cuò)誤都不至于影響運(yùn)算結(jié)果。 IBM為了突破極限，除了模擬大腦之外，還應(yīng)用了量子力學(xué)的原理，一直在致力于研究被稱為“非諾伊曼型”的新一代半導(dǎo)體。IBM認(rèn)為這次的成果是對(duì)約10年研究的重大總結(jié)，認(rèn)為將來(lái)有望開(kāi)發(fā)出以扭扣電池驅(qū)動(dòng)的郵票大小的超級(jí)計(jì)算機(jī)。

為了展示芯片至芯片的無(wú)縫通訊能力，IBM構(gòu)建出一款16芯片以單一網(wǎng)絡(luò)測(cè)試的電路板。
Source：IBMfD7esmc

本文授權(quán)編譯自EE Times，版權(quán)所有，謝絕轉(zhuǎn)載 本文下一頁(yè)：研究芯片可適應(yīng)現(xiàn)實(shí)世界的學(xué)習(xí)能力 {pagination} 該芯片采用三星(Samsung)的28nm制程制造，以實(shí)現(xiàn)高密度的芯片內(nèi)存與低泄漏晶體管性能。Modha表示該芯片第一次上電就能完美的運(yùn)作。 Modha 的公司目前正忙于開(kāi)發(fā)一款新的仿真器、新的編程語(yǔ)言、新的編程環(huán)境、新的工具庫(kù)、新的算法以及新的教學(xué)課程，旨在創(chuàng)造一個(gè)全球化的應(yīng)用生態(tài)系統(tǒng)。透過(guò)將操作數(shù)件移動(dòng)至更接近傳感器以及整合不同類型的傳感器，研究人員們希望能夠打造出具有更佳配備的neurosynaptic計(jì)算機(jī)，以便有效處理實(shí)時(shí)數(shù)據(jù)串流的多種意義。 “我們開(kāi)始與大學(xué)以及業(yè)界合作伙伴共同討論各種相關(guān)應(yīng)用，例如在相機(jī)上內(nèi)部對(duì)象辨識(shí)功能，或利用多傳感器融合來(lái)實(shí)現(xiàn)聽(tīng)覺(jué)處理，”Modha說(shuō)，”而在汽車和醫(yī)療設(shè)備中，可以采用收集的方式來(lái)處理數(shù)據(jù)，或者是能完全意識(shí)環(huán)境變化的智能手機(jī)等應(yīng)用?！?

該芯片的低功耗與感測(cè)處理性能使其相當(dāng)適于醫(yī)療、機(jī)器人、感測(cè)以及個(gè)人導(dǎo)航等多元化的應(yīng)用。
Source：IBMfD7esmc

IBM并致力于研究芯片可適應(yīng)現(xiàn)實(shí)世界變化的學(xué)習(xí)能力。該公司計(jì)劃利用在內(nèi)存密度方面的CMOS進(jìn)展、3D整合以及新的傳感器技術(shù)，以實(shí)現(xiàn)更低功耗、更緊密的封裝以及更快的速度。 這項(xiàng)研究計(jì)劃經(jīng)費(fèi)約5,300萬(wàn)美元，分為四個(gè)階段進(jìn)行，并由DARPA提供贊助。該計(jì)劃還將探索可在未來(lái)五年內(nèi)實(shí)現(xiàn)商用化的可能性。 本文授權(quán)編譯自EE Times，版權(quán)所有，謝絕轉(zhuǎn)載 編譯：Susan Hong 參考英文原文：IBM Puts Brain On-a-Chip，by R. Colin Johnson {pagination} IBM Puts Brain On-a-Chip R. Colin Johnson PORTLAND, Ore. -- The most brain-like computer chip to date has been produced by IBM for the Defense Advanced Research Project Agency's (DARPA's) Systems of Neuromorphic Adaptive Plastic Scalable Electronics (SyNAPSE) program, in collaboration with Cornell Tech and iniLabs, Ltd. "When the SyNAPSE project was launched six years ago, many people thought it was impossible," Dharmendra Modha, an IBM fellow and chief scientist of brain-inspired Computing at IBM Research, told EE Times. "But today we have proven that it is possible, and we are working toward making it a commercial reality in the future." The IBM SyNAPSE chip has 1 million artificial neurons (brain-like cells) and 256 million synapses (storage cells), all powered by 4,096 neurosynaptic cores integrating memory, computation, communication, and operating in an asynchronous event-driven, parallel, and fault-tolerant manner. IBM's neurosynaptic processor integrates 1 million neurons and 256 million synapses on a single silicon chip. (Source: IBM) "With 5.4 billion transistors, it is the biggest chip IBM has ever made, and as far as we know is the biggest chip anyone has ever made, and yet it consumes just 70 milliWatts of power," Modha said. To measure the performance of this mammoth chip, IBM had to invent a new metric, synaptic operations per second, (SOPS) to replace floating point operations per second (FLOPS). "The chip delivers 46 billion SOPS per Watt -- literally a supercomputer the size of a postage stamp, with the weight of a feather and using a power source the size of a hearing aide battery," Modha said. "It's ideal for monitoring sensors, mobile devices, executing cloud services, and supercomputing." The architecture consumes 20 milliWatts per square centimeter, which is more than 5,000 times cooler than the power required by today's microprocessors. This chip's architecture is based on an earlier chip with a single neurosynaptic core containing 256 neurons. In this second-generation chip, IBM reduced the area by 15 times, reduced the power by 100 times, and increased the number of cores per chip to 4,096. The cores are connected by an on-chip mesh network with direct connections between adjacent chips. When tiled, they seamlessly connect to one another in order to form a foundation for future neurosynaptic supercomputers. To demonstrate its scalability, IBM showed a 16-chip system which extended the architecture to 16 million programmable neurons and 4 billion programmable synapses, with the eventual goal of achieving human brain-sized systems of 100 trillion synapses or more. "We believe this chip establishes a new landmark in neurosynaptic computers with a radical new architecture, unparalleled scale, speed, power efficiency, and boundless scalability," Modha said. The layout of the chip (left) is composed of 64x64 array of neuro-synaptic cores, each of which (right) implements 256 neurons and 65,536 synapses for tightly integrated computation, memory, and communication. (Source: IBM) By integrating processing, memory, and communications on each core, IBM claims to have eliminated the dreaded von Neumann bottleneck that forces traditional microprocessors to resort to multiple levels of power-consuming caches. And since the cores all operate in parallel, they don't have to operate at power-consuming gigaHertz rates. In fact, the only clock on the chip is a 1kHz clock to discretize neuron dynamics. And by distributing the cores across the chip, the architecture is fault tolerant; any core can fail without affecting the outcomes of computations. To demonstrate the ability to connect chip-to-chip communication seamlessly through tiling, IBM build a board where 16 chips were tested as a single network. (Source: IBM) The chip was fabricated using Samsung's 28-nanometer process known for its dense on-chip memory and low-leakage transistors. Modha said it worked flawlessly the first time it was powered up. His company is busy creating a new simulator, a new programming language, a new programming environment, new libraries, new algorithms, and a new teaching curriculum aimed at creating a global ecosystem of applications. By moving the computing elements closer to the sensors and integrating different types of sensors, the hope is that neurosynaptic computers will be better equipped to deal with the ambiguity of real-time data streams. "We are beginning to talk to university and industrial partners about all sorts of applications, such as object recognition built into cameras, or auditory processing using multi-sensor fusion," Modha said. "And in automobiles or medical devices, the data could be processed as it is being collected, or smartphones that are totally aware of their environment." The low-power and sensory processing capabilities of this chip make it well suited for diverse applications (from left to right) in medicine (a smart thermometer that visually inspects the throat and sniffs for telltale odors of infection), robotics (an autonomous rolling robot studded with video cameras can inspect a disaster site), sensing (floating jellyfish-like sensors that measure water temperature, salinity, turbidity, and wave height) and personal navigation (assistive glasses that can help the visually impaired navigate complex environments). (Source: IBM) IBM is also working to demonstrate on-chip learning capabilities that adapt to the real world. It plans to take advantage of CMOS advances in memory density, 3-D integration, and new sensor technologies to enable even lower power use, denser packaging, and faster speeds. The funding totaled $53 million over four phases from DARPA. The program is exploring commercial possibilities that could be realized within the next five years.