摩爾定律(Moore's Law)將在未來的十年持續(xù)發(fā)展，但每單位晶體管成本下跌的速度將隨之減緩，無法再像過去一樣快速降低了。根據(jù)新思科技董事長兼首席執(zhí)行官Aart de Geus表示，芯片設(shè)計(jì)越來越復(fù)雜，逐漸推遲向更大晶圓的過渡，但也為其他替代技術(shù)開啟了大門。 Aart de Geus的這番評論正好出現(xiàn)在當(dāng)今業(yè)界日益關(guān)注半導(dǎo)體技術(shù)的未來發(fā)展之際。有些業(yè)界觀察家指出，28nm節(jié)點(diǎn)可能會是最后一次還能以新硅晶制程為客戶帶來完整的好處了──更低成本、功耗以及更高性能。 展望未來，“評判的標(biāo)準(zhǔn)將取決于每個(gè)晶體管成本降價(jià)的速度有多快──這同時(shí)也會是良率能多快提升的函數(shù)，”Aart de Geus指出，“隨著晶體管降價(jià)速度減緩，半導(dǎo)體的價(jià)格很可能就必須提高，”才能使芯片制造商得以回收投資。 不過，Aart de Geus也轉(zhuǎn)述英特爾資深院士Mark Bohr的看法，他說Mark Bohr表示看到一條可邁向7nm節(jié)點(diǎn)的發(fā)展道路，還“可能以某種方式降低每晶體管價(jià)格?！? 業(yè)界分析師G. Dan Hutcheson則指出，目前對于未來節(jié)點(diǎn)的每晶體管成本資料掌握有限。不過，根據(jù)以往的發(fā)展經(jīng)驗(yàn)，他預(yù)計(jì)業(yè)界將能持續(xù)看到成本下降。 Hutcheson指出，由于缺少下一代微影工具，晶圓廠自20nm起就必須為一些芯片層進(jìn)行兩次圖樣(pattern)過程。但微影技術(shù)僅占芯片制造成本的四分之一。 面對未來可能更高的成本，“業(yè)界將竭盡所能的利用目前的28nm節(jié)點(diǎn)，”Aart de Geus表示，“由于利潤并沒那么高，其他公司可能更指望在16/14nm節(jié)點(diǎn)，因此，只有一些廠商會轉(zhuǎn)移到20nm節(jié)點(diǎn)，”他補(bǔ)充說。 這可能會為其他替代技術(shù)開啟了另一扇門，如意法半導(dǎo)體(ST)以及其他業(yè)者提出的全耗盡型絕緣上覆硅(FD-SOI)技術(shù)。“但這也會帶動(dòng)其他主導(dǎo)廠商大力支持 FD-SOI ，”他說。 考慮到成本不斷的增加以及芯片制造的復(fù)雜度，半導(dǎo)體公司已經(jīng)將從300mm晶圓過渡到45nn晶圓的時(shí)程延遲到2020年了。Aart de Geus說：“更大的晶圓有時(shí)雖可帶來更低成本，但業(yè)界也相應(yīng)地需要一款完整的工具，如今卻還無法到位?！? 盡管如此，Aart de Geus對于未來發(fā)展仍抱持樂觀看法。隨著該公司推出重要的芯片設(shè)計(jì)軟件升級，他表示，“我們可支持多幾十億種晶體管芯片，而在未來十年也將看到持續(xù)的進(jìn)展?！? 有趣的是，在以Synopsys公司工具完成的設(shè)計(jì)中，只有約5%的設(shè)計(jì)采用目前先進(jìn)的28nm制程技術(shù)。根據(jù)Aart de Geus的簡報(bào)數(shù)據(jù)，180nm節(jié)點(diǎn)是目前最普遍的制程技術(shù)，在采用該工具的設(shè)計(jì)中約占30%，接著分別是65nm以及250nm節(jié)點(diǎn)。 “這的確是令人驚訝的數(shù)據(jù)分布，讓我不得不再三確認(rèn)圖表與數(shù)字是否確，”Aart de Geus說，“但可以確定的是我們看到了大量轉(zhuǎn)向28nm的趨勢，接下來也將逐漸增加過渡至16/14nm節(jié)點(diǎn)。”支持原創(chuàng)，鄙視抄襲，請?jiān)L問《國際電子商情》網(wǎng)站www.zgwwsyw.com 本文授權(quán)編譯自EE Times，版權(quán)所有，謝絕轉(zhuǎn)載 編譯：Susan Hong 參考英文原文：Transistor-Cost Declines Slowing, Synopsys Says，by Rick Merritt

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{pagination} Transistor-Cost Declines Slowing, Synopsys Says Rick Merritt SANTA CLARA, Calif. — Moore's Law will continue for the next decade, but declines in cost/transistor won't be as great as they were in the past, said Synopsys chairman Aart de Geus. Growing complexity of chip designs is delaying a shift to larger wafers and may open doors for alternative technologies, he said at an annual event for Synopsys users. His comments come at a time of increasing concern about the future of semiconductor technology. Some observers say the 28nm node could be the last to deliver the full range of benefits traditional with a new silicon node -- lower costs and power and higher performance. Looking ahead, "the jury is out in how fast price comes down per transistor -- that's a function of how quickly yields improve," de Geus told a press gathering here. "It is possible that as the price decrease of transistors lowers, the price of semiconductors has to go up" so chip makers can recoup their investments, he said. de Geus said he contacted Mark Bohr to get the Intel fellow's views. Bohr said he sees a path to a 7nm node and the "possibility of somehow lowering the price per transistor," de Geus reported. Analyst G. Dan Hutcheson said little data is available about the cost/transistor in future nodes. However, he is projecting the industry will continue to see cost declines based on its past history. Starting at 20nm, fabs have to pattern some chip layers twice due to the lack of next-generation lithography tools. But lithography only represents roughly a quarter of the cost of making a chip, Hutcheson said. Bunching up at 28nm In the face of potentially higher costs, "people will try to use today's 28nm node as much as they can," de Geus said. "Only a few people will move to the 20nm node [because its] benefits are not that high, so they will wait for 16/14nm nodes," he added. That could open the door to alternatives such as the fully depleted silicon-on-insulator technology proposed by STMicroelectronics and others. "But it would take [other] major players to put their weight behind" FD-SOI for it to take off, he said. Given the increasing costs and complexity of making chips, semiconductor companies have put off a shift from 300 to 450 mm wafers until 2020, he said. Larger wafers can sometimes provide lower costs but they also require "a complete retooling of the industry and that's not happening right now," he said. Nevertheless, the Synopsys executive remained upbeat at the event where he launched an upgrade of the company's main chip design software. "We support multiple billion-transistor chips, and we will see a continuation of that work for the next ten years," he said. Interestingly, only about five percent of the designs done in Synopsys' tools are at today's leading-edge 28nm process, according to one foil in de Geus's keynote. The 180nm node is the most popular, used by nearly 30% of the designs using its tools, followed by the 65nm and 250nm nodes. "It's an amazing spread -- I had to look twice at that graph to make sure the numbers were correct," de Geus said. "We do see the bulk of the designs gradually moving up and I think that will continue, but we will see a bunching up at 28nm and then slowly an increase to the 16/14nm nodes," he said.