作為PC和 服務器的I/O骨干技術(shù)， PCI Express (PCIe) 最近積極朝低功耗領(lǐng)域擴展，預計明年起將Ultrabook 、平板電腦(tablets)和智能手機都納入目標市場。這種強化的互連技術(shù)據(jù)稱能讓移動裝置在連接到高性能外圍，如 60GHz 無線網(wǎng)絡控制器和固態(tài)硬盤(SSD)時，降低兩倍到四倍的功耗。 PCI特別任務小組(PCI Special Interest Group)希望今年底前能通過針對 PCIe 3.0 底層軟件的新版規(guī)范。該程序代碼將執(zhí)行在由 MIPI 聯(lián)盟(MIPI Alliance)定義的M-PHY實體層芯片上，為移動裝置提供全新接口。 這兩大組織已于上周一(九月十日)簽署協(xié)議。PCI SIG將開發(fā)針對M-PHY的下一代PCIe 4.0軟件。 “低功耗版本的PCI Express一直是我們追求的目標，因為我們都知道，真正大量的消費者和大量的需求在哪里，”PCI SIG主席 Al Yanes說。 特別的是，PCI SIG將會定義其實體鏈接層軟件的變種，以便能執(zhí)行在M-PHY上。其程序代碼將可實現(xiàn)多個非對稱信道、動態(tài)頻寬協(xié)調(diào)，并大幅降低電磁干擾。 “我們設計讓移動裝置更容易導入 PCI Express，”MIPI聯(lián)盟副主席Brian Carlson說。 去夫，一位資深的 Marvell 公司工程經(jīng)理表示，希望用行動互連來將他的應用處理器連接到一個外部的 802.11ac 控制器。該連接必須能在1.8V供給電壓下達到1.1Gb/s速率、少于38milliwatts的功耗。 新的M-PHY結(jié)合了PCI Express，能滿足上述需求，Carlson說。在2011年4月定義的M-PHY速率為1.25Gb/s，而2012年6月公布的新版本速率則達到2.9Gb/s；預計明年發(fā)布的第三版還將推升到5.8Gb/s。 該連接在銅線上支持30公分，在光纜上支持5公尺距離。PCIe 3.0本身支持高達8 GTransfers/second速度。 2012年，預估將有超過30億個采用MIPI接口的裝置出貨，Carlson說。其中許多使用較舊型的D-PHY鏈接，執(zhí)行速度約500Mb/s，通常用于移動顯示器和相機等。 而新的PCIe over M-PHY則能滿足動態(tài)功耗、最大能量消耗等需求。PCI SIG今年6月針對PCIe 3.0發(fā)布新規(guī)范也滿足了英特爾在新一代處理器 Haswell 中納入的新閑置功耗技術(shù)要求。 本文授權(quán)編譯自EE Times，版權(quán)所有，謝絕轉(zhuǎn)載 編譯： Joy Teng 參考英文原文：Smartphone is next stop for PCI Express，by Rick Merritt

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{pagination} Smartphone is next stop for PCI Express Rick Merritt SAN FRANCISCO -- PCI Express, the I/O backbone of PCs and servers, is getting a low-power extension that will take it into Ultrabooks, tablets and smartphones starting next year. The enhanced interconnect will draw two to four times less power while helping mobile devices link to high-performance peripherals such as 60-GHz wireless networking controllers and solid-state drives. The PCI Special Interest Group expects to approve by the end of the year a new version of its low level software for PCIe 3.0. The code will run on the M-PHY physical layer chips defined by the MIPI Alliance that creates handset interfaces. The two groups signed a deal Monday (Sept. 10), cementing their collaboration. The PCI SIG will also create a version of its next-generation PCIe 4.0 software for M-PHY. “We’ve been chasing for months the Holy Grail of getting to a lower power version of PCI Express because we know that’s where the volume is and where the users are,” said Al Yanes, chairman of the PCI SIG. Specifically, the PCI SIG will define a new variant of its physical link layer software to run the M-PHY. The code will enable multiple asymmetrical lanes, dynamic bandwidth negotiation and lower electromagnetic interference. “We are making PCI Express mobile friendly,” said Brian Carlson, vice chairman of the MIPI Alliance. Last year, a senior Marvell engineering manager called for a mobile interconnect to link his applications processor to an external 802.11ac controller. The link needs to deliver 1.1Gbits/s while consuming less than 38 milliwatts on a 1.8-volt supply, he said. The new M-PHY combined with PCI Express addresses that need, said Carlson. M-PHY was first defined in April 2011 at 1.25 Gbits/s, an update released in June 2012 runs at 2.9 Gbits/s and a third generation coming next year will hit up to 5.8 Gbits/s. The link is defined over copper traces at up to 30 cm and over optical lengths up to five meters. For its part, PCIe 3.0 supports up to 8 GTranfers/second. As many as three billion devices using MIPI interfaces could ship in 2012, said Carlson. Many of them use an older D-PHY link, running at about 500 Mbits/s, geared for mobile displays and cameras. The new variant of PCIe over M-PHY addresses active power, the biggest consumer of energy. The PCI SIG released in June an addition to its PCIe 3.0 spec addressing idle power, a technology Intel incorporated into the design of its next-generation processor, Haswell.