GlobalFoundries 公司正在仔細(xì)考慮其 20nm 節(jié)點(diǎn)的低功耗和高性能等不同制程技術(shù)，而與此同時(shí)，多家芯片業(yè)高層也齊聚一堂，共同探討即將在2014年來臨的 3D IC ，以及進(jìn)一步往 7nm 節(jié)點(diǎn)發(fā)展的途徑。 IBM 的專家指出，下一代的20nm節(jié)點(diǎn)可支持最佳化的低功耗和高性能制程技術(shù)。而 GlobalFoundries 將在今年八月決定，是否提供這些不同的制程選項(xiàng)。 這些僅僅是今年度 GSA Silicon Summit 上討論的兩個(gè)焦點(diǎn)。與會(huì)的芯片業(yè)高層還討論了預(yù)計(jì)在2014年到來，但仍面臨諸多挑戰(zhàn)的 3D IC ，以及腳步緩慢但仍然預(yù)見可朝 7nm 邁進(jìn)的 CMOS 微縮技術(shù)。 “臺(tái)積電最近表示其 20nm 節(jié)點(diǎn)在制程最佳化方面并沒有顯著差異，但我并不這么認(rèn)為，” IBM 院士暨微電子部門首席技術(shù)專家Subramanian Iyer說。“我相信，在相同的節(jié)點(diǎn)上，你可以擁有兩種不同的制程，”他在主題演講中表示。 事實(shí)上， GlobalFoundries 正在考慮是否是在為 20nm 提供高性能和低功耗制程。 “我們?nèi)栽谂c主要客戶討論該做些什么，針對(duì)性能和功耗方面，可能要做出更多取舍，” GlobalFoundries 先進(jìn)技術(shù)架構(gòu)主管Subramani Kengeri表示。 他指出， 20nm 的變化空間可能相對(duì)更加狹小，而且從經(jīng)濟(jì)面來看也未必可行。IBM的Iyer則認(rèn)為，臺(tái)積電決定僅提供一種20nm制程，其經(jīng)濟(jì)面的考量可能多于技術(shù)面。 接下來，采用FinFET的14nm制程，則將為芯片產(chǎn)業(yè)開創(chuàng)更大的機(jī)會(huì)，如提供0.9V的高性能版本，以及0.6V的低功耗變種制程等。此外，與傳統(tǒng)轉(zhuǎn)移到一個(gè)新制程節(jié)點(diǎn)相較，14nm節(jié)點(diǎn)可提供的利益也預(yù)估將高出兩倍之多。 從歷史角度來看，要為每一個(gè)節(jié)點(diǎn)提供不同制程變化，都會(huì)需要在基礎(chǔ)制程上添加獨(dú)特且復(fù)雜的特性，IBM的Iyer說。他指出，過去，我們?cè)诿恳淮瞥坦?jié)點(diǎn)都擁有不同功能的制程，現(xiàn)在不大可能驟然讓它們完全消失。

20nm仍有變化空間，Subramanian Iyer說。3YZesmc

本文下一頁：2014年，迎接3D IC到來 本文授權(quán)編譯自EE Times，版權(quán)所有，謝絕轉(zhuǎn)載

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{pagination} 2014年，迎接3D IC到來 此外，芯片業(yè)高層也探討了幾種可望在2014年量產(chǎn)，采用硅穿孔(TSV)的3D IC。 思科系統(tǒng)(Cisco Systems)封裝專家暨技術(shù)品質(zhì)部副總裁Mark Brillhart表示，3D IC將改變游戲規(guī)則。他認(rèn)為3D IC將有幾種不同的形式，而且很快就會(huì)步入大量應(yīng)用。 “自1996年的覆晶封裝技術(shù)熱潮以來，我從未想象過封裝技術(shù)能再次令人感到振奮，”Brillhart說。 高通(Qualcomm)“非常高興”能在實(shí)驗(yàn)室中采用Xilinx的2.5D FPGA來開發(fā)原型，高通工程部副總裁Nick Yu表示。他預(yù)計(jì)，運(yùn)用TSV來鏈接Wide I/O的高階智能手機(jī)用行動(dòng)應(yīng)用處理器最快今年或明年便可問世。 “我們會(huì)在許多不同領(lǐng)域看到這些強(qiáng)大的3D技術(shù)，”IBM的Iyer表示，他們已經(jīng)制造出了數(shù)款使用TSV堆棧處理器和DRAM的原型產(chǎn)品。 目前的CPU有8～12個(gè)核心，未來還將朝采用3D IC技術(shù)，堆棧24個(gè)核心與DRAM還有散熱片的方向發(fā)展。IBM也對(duì)于‘在硅中介層上建構(gòu)系統(tǒng)’(system on an interposer)的2.5D模塊深感興趣，在這些模塊中，內(nèi)存芯片在硅基板上圍繞著處理器而建置，并使用去耦電容來改善功率調(diào)節(jié)性能。 “這個(gè)領(lǐng)域不斷出現(xiàn)更多的創(chuàng)新，它們將帶來更顯著的差異化，但共同點(diǎn)在于它們都將提供適合行動(dòng)應(yīng)用的優(yōu)勢(shì)，”他補(bǔ)充說。 但3D芯片仍有許多待解的難題。工程師仍不知如何解決3D IC產(chǎn)生的熱問題，他們需要新的測(cè)試策略和制造工具，他們也正在推動(dòng)各領(lǐng)域的設(shè)計(jì)師們形成新的供應(yīng)鏈，就各種技術(shù)和商業(yè)問題展開深入合作及探索。 “現(xiàn)階段，成本是3D芯片面臨的最大問題，”高通的Yu表示。 他表示，臺(tái)積電提出的端對(duì)端(end-to-end) 3D服務(wù)會(huì)是低成本的說法并不能讓他信服。他進(jìn)一指出，不同的3D產(chǎn)品會(huì)需要不同的供應(yīng)鏈。 “設(shè)備占單位成本很大一部份，”日月光集團(tuán)(ASE Group)工程暨業(yè)務(wù)部資深副總裁Rich Rice說。該公司正在安裝接合╱分離(bonding/de-bonding)、晶圓薄化和其它負(fù)責(zé)處理所謂3D制程中間步驟的設(shè)備?！凹词故窃谳^傳統(tǒng) 的后段制程領(lǐng)域，當(dāng)我們決定量產(chǎn)，我們也必須擔(dān)負(fù)必要的資本支出，”Rice說。 應(yīng)用材料(Applied Materials)發(fā)言人指出，業(yè)界需要新的3D系統(tǒng)，設(shè)備制造商正在努力準(zhǔn)備為450mm晶圓和20、14nm節(jié)點(diǎn)做準(zhǔn)備。 思科的Brillhart表示，他擔(dān)憂的事情還有很多，包括為了找到讓3D芯片獲利的可行方法，彼此競(jìng)爭(zhēng)的公司有時(shí)也必須合作。 本文下一頁：摩爾定律步伐緩慢 本文授權(quán)編譯自EE Times，版權(quán)所有，謝絕轉(zhuǎn)載

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{pagination} 摩爾定律步伐緩慢 好消息是，專家們認(rèn)為，一直到至少7nm節(jié)點(diǎn)，都不會(huì)出現(xiàn)根本性的障礙。但壞消息則是“更微小節(jié)點(diǎn)的優(yōu)勢(shì)正不斷被侵蝕，”IBM的Iyer說。 罪魁禍?zhǔn)拙臀⒂凹夹g(shù)。今天業(yè)界采用的193nm浸入式微影技術(shù)已經(jīng)被要求用在22甚至14nm節(jié)點(diǎn)。 “這導(dǎo)致了愈來愈高的成本，”Iyer說?！傲硗?，復(fù)雜的圖形解決方案也讓我們感到焦慮?！?微影成本確實(shí)會(huì)在20nm和14nm節(jié)點(diǎn)劇烈飆升，GlobalFoundries的Kengeri表示。他指出，額外的復(fù)雜性以及制程和設(shè)計(jì)成本，是讓傳統(tǒng)芯片產(chǎn)業(yè)每兩年跨越一個(gè)技術(shù)世代的時(shí)程開始延長的主要原因之一。 業(yè)界多花費(fèi)了三季的時(shí)間來達(dá)到符合品質(zhì)要求的32/28nm技術(shù)節(jié)點(diǎn)，這要比過去所花費(fèi)的時(shí)間多出一季，Kengeri說。“可看到整個(gè)產(chǎn)業(yè)的腳步正在趨緩，”他表示。 根據(jù)美林(Merrill Lynch)的報(bào)告，一個(gè)14nm的SoC項(xiàng)目成本可能會(huì)上揚(yáng)到2.5億美元，Marvell Semiconductor制造部副總裁Roawen Chen說。光罩成本約700萬美元，且從投片到產(chǎn)出首個(gè)硅芯片的時(shí)間可能會(huì)延長到六個(gè)月，他表示。 “事實(shí)是它將變得更加昂貴，”Chen說。 但也有好消息，IBM的研究人員已經(jīng)發(fā)現(xiàn)了制造出僅內(nèi)含25個(gè)原子組件的方法，這為邁向7nm制程節(jié)點(diǎn)開啟了全新道路?！霸诔?nm前進(jìn)的道路上，我們并沒有看到根本性的問題存在，”Iyer說。 編譯： Joy Teng 本文授權(quán)編譯自EE Times，版權(quán)所有，謝絕轉(zhuǎn)載 參考英文原文： Chip execs see 20 nm variants, 3-D ICs ahead ，by Rick Merritt

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{pagination} Chip execs see 20 nm variants, 3-D ICs ahead Rick Merritt MOUNTAIN VIEW, Calif. – Next-generation 20 nm processes can support optimized versions for low power and high performance, according to an IBM expert. GlobalFoundries will decide in August whether or not it will offer such variations. Those were just two data points from wide ranging discussions at the GSA Silicon Summit here. Separately, executives said a variety of 3-D ICs will hit the market in 2014 despite numerous challenges, and CMOS scaling is slowing down but still viable through a 7 nm node. “Recently TSMC said at 20 nm there are no significant differences [in process optimizations], but I don’t believe that,” said Subramanian Iyer, an IBM fellow and chief technologist in its microelectronics division. “I believe at same node you can have two [different variations],” he said in a keynote here. Indeed, GlobalFoundries is debating whether it wants to offer high performance and low power variants of a 20 nm process it is putting in place today. “We are still talking with lead customers to see what is the right thing to do, and there’s a lot of interest in performance and power trade-offs,” said Subramani Kengeri, head of advanced technology architecture at GlobalFoundries in a brief interview with EE Times. The variations available at 20 nm may be relatively narrow and may not be economically viable, he said. Iyer of IBM said TSMC’s decision to offer one flavor of 20 nm may have been more of an economic than a technical decision. The follow-on 14 nm process using FinFETs will open up greater opportunities for a high performance version at up to 0.9 volts and a low power variant at down to 0.6 volts, Kengeri said. In addition, the 14 nm node could offer as much as twice the typical benefits of moving to a new node. The historic challenge of offering variations of a process is that each one requires a different set of unique and complex features added to the base process, said Iyer of IBM. “All the little features we have are like drugs, we can’t drop them without severe withdrawal symptoms,” he said. 3-D ICs coming in 2014 Separately, executives said several types of 3-D ICs using through-silicon vias (TSVs) will be in production in 2014. “This is a game changer,” said Mark Brillhart, a packaging expert and vice president of technology and quality at Cisco Systems, moderating a panel here. “I think 3-D ICs will be a differentiator and they will proliferate into a lot of applications,” he said. “I never thought packaging would be exciting again, but it’s like 1996 with flip chip all over again,” Brillhart said. Qualcomm is “very happy with” dense 2.5-D Xilinx FPGAs “we are playing with in the lab” for product prototyping, said Nick Yu, vice president of engineering at Qualcomm. He predicted mobile applications processors for high-end smartphones will hit the market this year or next using TSVs to link to Wide I/O memories. “This 3-D technology is really powerful and we will see it in many places,” said Iyer of IBM which has already made working prototypes of server processors in TSV stacks with DRAMs. CPUs have 8-12 cores now “and want to go to 24 cores” with 3-D IC modules that stack DRAMs and heat sinks. IBM is also interested in “systems on an interposer,” 2.5-D modules that surround a processor with memory chips on a silicon substrate with de-coupling capacitors to improve power regulation, he said. “There’s a lot of good stuff happening in this area that will make a significant difference, and the same concepts are applicable in the mobile space with similar advantages,” he added. The 3-D ICs also pose plenty of unsolved problems. They generate heat that engineers still don’t know how to dissipate, they require new test strategies and manufacturing tools and they require designers form new kinds of supply chains that collaborate on deeply detailed technical and business levels. “Cost is biggest issue of 3-D ICs right now,” said Yu of Qualcomm. He said he is not convinced TSMC’s proposed end-to-end 3-D service will be the lowest cost offering it promises. Different supply chains will be required for different 3-D products, he added. “Equipment costs are a big factor in our unit costs,” said Rich Rice, senior vice president of engineering and sales at ASE Group which is installing bonding/de-bonding, wafer thinning and other systems to handle the so-called middle steps of the 3-D process. “Even on the more traditional back-end we have a stiff cap ex burden when we start to ramp this capability up,” Rice said. A spokesman for Applied Materials noted the need for new 3-D systems comes while capital equipment makers are also trying to prepare systems for 450 mm wafers and the 20 and 14 nm nodes. Cisco’s Brillhart said he is concerned the many sometimes competing companies that need to come together to enable 3-D ICs find profitable ways to collaborate. “I’ve worked on too many programs where one of the partners in the supply chain became unprofitable and the technology went away,” he said. Moore’s Law more slowly The good news is experts see no fundamental barriers to scaling process technology down to at least 7 nm. The bad news is “as you go to smaller nodes the benefits of scaling are being eroded significantly,” said Iyer of IBM. The culprit is the lack of any new lithography techniques. Today’s 193 nm immersion lithography systems are being asked to create 22 and even 14 nm features. “This does not come free, the costs are becoming formidable,” Iyer said. “Complex patterning solutions are the cause of the angst we are having,” he added. Indeed costs of lithography will jump significantly at 20 nm and soar at 14 nm, said Kengeri of GlobalFoundries. The additional complexities and process and design costs are among the reasons the traditional two-year cadence between nodes is lengthening, he said. It took three extra quarters for the industry to qualify the 32/28 nm node and the ramp for the technology was a quarter longer than usual, Kengeri said. “Things are slowing down,” he added. According to a Merrill Lynch report, the cost of a single SoC project could bloat to $250 million at the 14 nm node, said Roawen Chen, vice president of manufacturing at Marvell Semiconductor. Masks costs alone will be about $7 million and the time from tapeout to first silicon could expand to six months, he said. “The bottom line is its becoming very expensive,” Chen said. The good news is one IBM researcher showed ways to make devices with as few as 25 atoms, opening the door to a 7 nm, process node. “Until we get to 7 nm or so there are no fundamental issues we see,” said Iyer.