在英特爾(Intel)負責制程技術(shù)部門的高層Mark Bohr指出，無晶圓廠(fabless)半導體業(yè)經(jīng)營模式已經(jīng)快到窮途末路。他認為，臺積電(TSMC)最近宣布只會提供一種20nm制程，就是一種承認失敗的表示；而且該晶圓代工大廠顯然無法在下一個主流制程節(jié)點提供如 3D晶體管所需的減少泄漏電流技術(shù)。
“高通(Qualcomm)不能使用那種(22nm)制程技術(shù)；”Bohr在日前于美國舉行的 Ivy Bridge 處理器發(fā)表會上宣布，該新款處理器是采用英特爾三閘22nm制程生產(chǎn)。他在會后即興談話中對筆者表示：“晶圓代工模式正在崩壞?！?當然，英特爾會想讓這個世界相信，只有他們能創(chuàng)造世界所需的復雜半導體技術(shù)，而為其競爭對手高通、AMD代工的臺積電與GlobalFoundries都不能。在Ivy Bridge處理器發(fā)表會上，英特爾所述說的公司成功故事，其秘訣之一就是來自于制程技術(shù)與芯片設計者之間的緊密關(guān)系。
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英特爾客戶端PC事業(yè)群新任總經(jīng)理Kirk Skaugen在發(fā)表會上與Bohr、還有Ivy Bridge項目經(jīng)理Brad Heaney一同主持問答時間；這款處理器除了首度采用3D晶體管架構(gòu)，也是英特爾第一次以High-K金屬閘極制程制造的產(chǎn)品?！白鳛橐患艺辖M件制造廠(IDM)，確實有助于我們解決生產(chǎn)這樣一款小尺寸、復雜組件時所遭遇的問題?！盉ohr表示。
在當下我沒有質(zhì)疑他的說法。自從進入次微米制程時代，EETimes美國版就有不少文章談到芯片設計業(yè)者與制程技術(shù)提供者之間，需要有更緊密的合作關(guān)系；一位來自Nvidia的實體設計部門高層也在最近Mentor Graphics的年度會議上，強調(diào)了相同的論點。
不過，Bohr在指稱晶圓代工廠與無晶圓廠芯片設計業(yè)者無法追隨英特爾的腳步時，似乎是過度延伸了該論點。筆者聽過臺積電與GlobalFoundries 的研發(fā)主管提出很好的例子，證明3D晶體管架構(gòu)在14nm制程節(jié)點之前并非必要；臺積電并曾表示，20nm節(jié)點并沒有足夠的回旋空間，可創(chuàng)造高性能制程與低耗電制程之間的明顯變化。
本文下一頁：高通缺貨說明了一些問題
本文授權(quán)編譯自EE Times，版權(quán)所有，謝絕轉(zhuǎn)載
相關(guān)閱讀：
• 28nm產(chǎn)能告急，高通大訂單花落誰家
• 兩岸半導體廠商合作，才能御外敵
• 2012晶圓代工收入可增長12%，但面臨三大挑戰(zhàn)E2fesmc
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我忘了問Bohr英特爾是否已在22nm節(jié)點將高性能制程(high performance)與低耗電(low power)制程做區(qū)別，不過他在問答時表示，英特爾已經(jīng)完成了一個特別針對SoC組件生產(chǎn)的制程技術(shù)版本，該公司計劃在每個主流制程技術(shù)完成后，進一步于一季或是兩季之后推出該SoC版本的變形。
對于臺積電的20nm制程計劃，高通不會發(fā)表評論；但高通確實在最近財務季報發(fā)表會上表示，該公司無法向臺積電取得足夠的28nm制程產(chǎn)能以因應市場需求，因此正尋求多個新代工來源，并預期能在今年稍晚正式上線。
這對GlobalFoundries、聯(lián)電(UMC)等其它代工廠來說是個好機會；不過Bohr認為，由于生產(chǎn)28nmSoC需要在設計細節(jié)上有更緊密的交流，對高通來說，與同樣有生產(chǎn)手機SoC (Exynos)的競爭對手三星(Samsung)的代工伙伴合作，其風險會大過于任何機會。
筆者詢問Bohr，英特爾除了提供22nm制程給兩家已公開的伙伴Achronix 與 Netronome之外，是否還有其它的合作對象；但他只回答，英特爾并不想涉足晶圓代工業(yè)務，只是讓少數(shù)幾家策略伙伴取得其技術(shù)。
英特爾可能沒辦法獨占聰明的制程工程師或設計工程師，但顯然擁有一些杰出的員工，已學會如何巧妙地自我行銷；Bohr與Heaney就現(xiàn)身于發(fā)表會上放映的搞笑影片中，他們兩個被微縮，進入一顆Ivy Bridge芯片中游歷。
展望未來，Bohr表示英特爾已經(jīng)使用浸潤式微影技術(shù)，完成下一代14nm節(jié)點制程的特性描述；其成果不只是“令人振奮”而已，也意味著該公司可望將浸潤式微影技術(shù)運用到仍在初期計劃階段的10nm節(jié)點：“我們認為已經(jīng)找到在10nm節(jié)點運用浸潤式微影技術(shù)的解決方案──我們也很樂意使用超紫外光(EUV)微影技術(shù)，但不抱太大期望?！?
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接著筆者又問道，英特爾是否會在14與10nm節(jié)點擁有一些像是3D晶體管這樣的新花招，他簡單回答：“是?！薄斠患夜举潛P其高階工程師并提供與他們接觸的機會時，真的是很不錯，但我實在是很不愛看到這些人被一家公司的公關(guān)部門“訓練有素”的模樣。
編譯：Judith Cheng
本文授權(quán)編譯自EE Times，版權(quán)所有，謝絕轉(zhuǎn)載
參考英文原文：Intel exec says fabless model “collapsing”，by Rick Merritt
相關(guān)閱讀：
• 28nm產(chǎn)能告急，高通大訂單花落誰家
• 兩岸半導體廠商合作，才能御外敵
• 2012晶圓代工收入可增長12%，但面臨三大挑戰(zhàn)E2fesmc
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Intel exec says fabless model 'collapsing'
Rick Merritt
SAN FRANCISCO – It’s the beginning of the end for the fabless model according to Mark Bohr, the man I think of as Mr. Process Technology at Intel.
Bohr claims TSMC’s recent announcement it will serve just one flavor of 20 nm process technology is an admission of failure. The Taiwan fab giant apparently cannot make at its next major node the kind of 3-D transistors needed mitigate leakage current, Bohr said.
“Qualcomm won’t be able to use that [20 nm] process,” Bohr told me in an impromptu discussion at yesterday’s press event where Intel announced its Ivy Bridge CPUs made in its tri-gate 22 nm process. “The foundry model is collapsing,” he told me.
Of course Intel would like the world to believe that only it can create the complex semiconductor technology the world needs. Not TSMC that serves competitors like Qualcomm or GlobalFoundries that makes chips for Intel’s archrival AMD.
Intel used the Ivy Bridge event to spin the tale of how part of the secret to its success is its close partnership between process and chip designers.
Kirk Skaugen, the new general manager of Intel’s client PC group, moderated a Q&A with Bohr and Brad Heaney, the Ivy Bridge program manager. In addition to working together on Intel’s first CPUs using 3-D transistors, the two collaborated on Intel’s first processors using high-K metal gate technology.
“Being an integrated device manufacturer really helps us solve the problems dealing with devices this small and complex,” Bohr said in the Q&A.
I don’t doubt that for a minute. Since the dawn of submicron design, EE Times has been writing about the need for ever closer collaboration between chip and process designers. An Nvidia physical design exec underlined the same point in a recent talk at Mentor Graphics’ annual user group meeting.
But Bohr stretches the point too far when he says the foundries and fabless companies won’t be able to follow where Intel is going. I have heard top TSMC and GlobalFoundries R&D managers make a good case that 3-D transistors won’t be needed until the 14 nm generation. For its part, TSMC said at 20 nm there is not enough wiggle room to create significant variations for high performance versus low power processes.
I neglected to ask Bohr whether Intel has separate high performance and low power processes in its 22 nm technology. (Anyone from Intel is welcome to chime in here.)
However, in an open Q&A, Bohr said Intel has completed work on an SoC-specific version of its process technology. It plans going forward to have an SoC variant a quarter or two after each main process is complete.
For its part, Qualcomm would not provide its opinions on TSMC’s 20 nm plans. The company did say in its recent quarterly earnings call it can’t get enough 28 nm technology from TSMC to meet product demand, so it is working to develop multiple new sources it expects will come online later this year.
That’s a big opportunity for a GlobalFoundries, UMC or other fabs to step up. Given the close sharing of design details required to make 28 nm SoCs, it’s more of a risk than an opportunity for Qualcomm to work with Samsung’s foundry folks, Bohr said, given Samsung has its own Exynos mobile SoCs.
I asked Bohr to whom Intel is providing access to its 22 nm process besides two announced partners—Achronix and Netronome. He only said that Intel does not want to be in the general foundry business, but it makes its technology available to a few strategic partners.
Intel has no monopoly on smart process technology engineers and designers. But it does have some brilliant ones, and it has learned to market them smartly. Bohr and Heaney even appeared yesterday in another one of Intel’s playful videos shrinking the two engineers so they could tour the insides of an Ivy Bridge chip.
Looking ahead, Bohr said Intel has finished characterizing its next-generation 14 nm process using immersion lithography. It even has “encouraging results” suggesting it will be able to use immersion litho for the 10 nm node that is still in early planning phase.
“We think we have a [10nm] solution using immersion lithography—we’d love to have extreme ultraviolet [EUV] lithography, but we are not counting on it,” said Bohr in the event Q&A.
As a follow up, I asked whether Intel has other new process tricks like 3-D transistors at 14 and 10 nm. His answer: “Yes!”
I love it when companies celebrate and provide access to their top engineers. But I hate it when they are so well trained by their PR departments.
