晶圓代工大廠臺(tái)積電(TSMC)資深研發(fā)副總裁蔣尚義(Shang-Yi Chiang)在日前于美國(guó)舉行的ARM技術(shù)論壇(TechCon)上表示，在接下來十年以FinFET技術(shù)持續(xù)進(jìn)行半導(dǎo)體制程微縮的途徑是清晰可見的，可直達(dá) 7nm節(jié)點(diǎn)；但在 7nm節(jié)點(diǎn)以下，半導(dǎo)體制程微縮的最大挑戰(zhàn)來自于經(jīng)濟(jì)，并非技術(shù)。
蔣尚義表示，他有信心半導(dǎo)體產(chǎn)業(yè)將在接下來十年找到克服7nm以下節(jié)點(diǎn)技術(shù)障礙的解決方案；但也指出，新技術(shù)雖然能實(shí)現(xiàn)7nm以下節(jié)點(diǎn)制程芯片量產(chǎn)，卻可能得付出高昂代價(jià)：“當(dāng)制程節(jié)點(diǎn)演進(jìn)，我們也看到晶圓制造價(jià)格比前一代制程增加了許多。”
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在ARM技術(shù)論壇的另一場(chǎng)專題演說中，EDA供貨商Cadence Design Systems旗下Silicon Realization部門的資深研發(fā)副總裁徐季平(Chi-Ping Hsu)，演示文稿了半導(dǎo)體制程從32/28nm節(jié)點(diǎn)過渡到22/20nm節(jié)點(diǎn)的制程技術(shù)研發(fā)成本增加幅度；他舉例指出，如果32/28nm節(jié)點(diǎn)需成本是12億美元，來到22/20nm節(jié)點(diǎn)，該成本規(guī)模將增加至21至30億美元。
至于芯片設(shè)計(jì)成本，則會(huì)從32nm節(jié)點(diǎn)所需的5,000萬至9,000萬美元，在22nm節(jié)點(diǎn)增加至1.2億至5億美元。徐季平并指出，在32nm節(jié)點(diǎn)，芯片銷售量需要達(dá)到3,000至4,000萬顆，才能打平成本；但到了20nm節(jié)點(diǎn)，該門檻會(huì)提高至6,000萬至1億顆。
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FinFET是一種 3D晶體管技術(shù)，目前正初步獲得芯片制造商的采用；大廠英特爾(Intel)則是將其3D晶體管技術(shù)稱為“三閘(tri-gate)”，業(yè)界預(yù)計(jì)該公司將在今年底推出采用3D晶體管技術(shù)所生產(chǎn)的22nm芯片樣品。
蔣尚義表示，22nm節(jié)點(diǎn)會(huì)是半導(dǎo)體產(chǎn)業(yè)采用平面晶體管技術(shù)(planar transistor)的最后一個(gè)時(shí)代：“在此之后，該技術(shù)就會(huì)功成身退。”
編譯：Judith Cheng
本文授權(quán)編譯自EE Times，版權(quán)所有，謝絕轉(zhuǎn)載
參考英文原文：TSMC's R&D chief sees 10 years of scaling，by Dylan McGrath
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TSMC's R&D chief sees 10 years of scaling
DylanMcGrath
SANTA CLARA, Calif.—The path is clear for continued semiconductor scaling using FinFETs for the next decade, down to the 7-nm node, according to Shang-Yi Chiang, senior vice president of R&D at foundry giant Taiwan Semiconductor Manufacturing Co.
Beyond 7-nm, the most pressing challenges to continued scaling will come from economics, not technology, Chiang said in a keynote address at the ARM TechCon event here Tuesday (Oct. 25).
Chiang (above) said he has faith that the semiconductor industry will solve technical hurdles associated with moving past 7-nm over the next decade, but acknowledged that the new technologies might make volume manufacturing of chips with critical dimensions smaller than 7-nm cost prohibitive.
"From node to node, we have found the wafer price has increased much more than previous nodes," Chiang said.
In another ARM TechCon keynote later, Chi-Ping Hsu (right), senior vice president of R&D at in EDA vendor Cadence Design Systems Inc.'s Silicon Realization Group, presented data on dramatic cost increases associated with moving from the 32/28-nm node to the 22/20-nm node. The amount of money invested by the semiconductor industry in process R&D, for instance, jumped from $1.2 billion at 32/28 to between $2.1 billion and $3 billion at 22/20, Hsu said. Design costs for a chip jump from $50 million to $90 million at 32-nm to $120 million to $500 million at 22-nm, Hsu said.
At the 32-nm node, a chip needs to sell about 30 to 40 million units to recoup the costs associated with it, Hsu said. At the 20-nm node, the "breakeven" point jumps to between 60 and 100 million units, Hsu said.
FinFETs are three-dimensional transistors in the early stages of being adopted by chip makers. Intel Corp., which refers to its 3-D transistor technology as "tri-gate," is expected to begin sampling 22-nm chips with 3-D transistors later this year.
Chiang said the 20-nm node will be the last generation at which the semiconductor industry can possibly use a planar transistor. "After that, it will run out of steam," Chiang said.
