據(jù)臺(tái)灣對(duì)外貿(mào)易發(fā)展協(xié)會(huì)(TAITRA)透露，芯片代工巨頭臺(tái)積電（TSMC）有望超過intel，在2011年底推出業(yè)內(nèi)首款采用3-D芯片堆疊技術(shù)的半導(dǎo)體芯片產(chǎn)品。 TAITRA的報(bào)告援引了一則匿名消息： Intel曾于今年5月表示，他們將于今年年底前開始量產(chǎn)結(jié)合了三門晶體管技術(shù)（臺(tái)積電計(jì)劃14nm節(jié)點(diǎn)啟用類似的Finfet技術(shù)）的芯片產(chǎn)品。而臺(tái)積電這次推出采用3-D芯片堆疊技術(shù)半導(dǎo)體芯片產(chǎn)品的時(shí)間點(diǎn)則與其非?？拷?。 雖然臺(tái)積電在與intel的3-D芯片競速比賽中獲勝了，但需要說明的是，臺(tái)積電采用的技術(shù)與Intel的三門晶體管技術(shù)存在很大的區(qū)別。臺(tái)積電開發(fā)的3-D芯片堆疊技術(shù)與其它半導(dǎo)體廠商一樣，以穿硅互聯(lián)技術(shù)（TSV）為核心 ，通過在互聯(lián)層中采用TSV技術(shù)來將各塊芯片連接在一起，以達(dá)到縮小芯片總占地面積，減小芯片間信號(hào)傳輸距離的目的。而英特爾采用的三門晶體管技術(shù)則是從芯片的核心部分晶體管內(nèi)部結(jié)構(gòu)上進(jìn)行改革，業(yè)界稱為FinFET，因?yàn)楣柰ǖ李愃朴谝粋€(gè)從半導(dǎo)體基片上凸起來的鰭。 根據(jù)外貿(mào)協(xié)會(huì)的報(bào)告，3-D技術(shù)等效增大了單芯片中的晶體管密度高達(dá)1000倍，而能耗則可降低50％左右。新技術(shù)有望解決傳統(tǒng)的“平面”的晶體管遇到的只能二維移動(dòng)電子的困難。 在增加芯片單位面積內(nèi)的晶體管密度方面，3-D芯片堆疊技術(shù)和三門晶體管技術(shù)均能起到正面的影響作用。 TAITRA還引用了臺(tái)積電研發(fā)部門高級(jí)副總裁蔣尚義的話稱，臺(tái)積電一直都在與芯片封裝商，以及芯片自動(dòng)化設(shè)計(jì)軟件開發(fā)商就改善3-D芯片堆疊技術(shù)的實(shí)用性方面進(jìn)行緊密合作。 編譯：Luffy Liu 本文授權(quán)編譯自EE Times， 版權(quán)所有，謝絕轉(zhuǎn)載 參考英文原文：Report: TSMC may beat Intel to 3-D chips, by Dylan McGrath

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{pagination} Report: TSMC may beat Intel to 3-D chips Dylan McGrath BATTLE MOUNTAIN, Nev.—Chip foundry giant Taiwan Semiconductor Manufacturing Co. (TSMC) could deliver its first semiconductors with 3-D interconnects by the end of 2011, potentially beating Intel Corp. to the punch in offering the first 3-D chips, according to a report circulated Tuesday (July 5) by a Taiwan trade group. The report by the Taiwan External Trade Development Council (TAITRA) quoted an anonymous source saying that TSMC's projected delivery of 3-D chips matches that of Intel, the world's biggest chip maker. Intel announced with great fanfare in May that it would begin high-volume production of 3-D chips using tri-gate transistors by the end of the year. While the TAITRA report pits TSMC against Intel in a race to produce the first 3-D chips, the technologies at issue are actually quite different. TSMC and others have for some time been developing technology for chips with 3-D interconnect, called through silicon vias (TSVs)--vertical connections that pass through die to connect different layers of a chip within the same package. Intel's tri-gates are actually 3-D transistors, known outside Intel as a FinFets because the silicon channel is akin to a fin jutting up from the semiconductor substrate. According to the TAITRA report, 3-D technology boosts the density of transistors in a single chip by up to 1,000 times. The 3-D devices are also expected to consume about 50 percent less energy. The new technology is expected to override a number of difficulties posed by traditional "planar" transistors, which can only move electrons across two dimensions, according to the report. Shang-Yi Chiang, senior vice president for R&D at TSMC, was quoted in the TAITRA report saying TSMC has been working closely with chip packagers and providers of design auto software to commercialize 3-D chip technology.